EP910PI-20T vs EP910PI-30T Comparison
Detailed side-by-side comparison of EP910PI-20T by Intel and EP910PI-30T by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP910PI-20T | EP910PI-30T |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device | EP910 | — |
| Number of Macrocells | 24 | — |
| Number of Usable Gates | [DATA_NEEDED: usable gate count] | — |
| Propagation Delay (tpd) | 20 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Number of Dedicated Inputs | 12 | — |
| Number of I/O Pins | 20 | — |
| Number of Pins | 40 | — |
| Package | PDIP-40 (PI) | — |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| Technology | CMOS EPROM (UV-erasable) | CMOS, UV-erasable (windowed ceramic) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (industrial) |
| Programming | Standard EPROM programmer, JEDEC map | Altera Classic device programmer / MAX+PLUS II flow |
| RoHS Status | unknown | [DATA_NEEDED: RoHS status] |
| Lifecycle Status | Not Recommended for New Designs (NRND) | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 24 |
| Usable Gates | — | 480 |
| Dedicated Inputs | — | 10 |
| Propagation Delay (tPD) | — | 30 ns |
| Register (Clock-to-Output) Delay | — | 20 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Package Type | — | 40-pin PDIP (ceramic windowed) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |