EPC144LC20 vs EPC1LC20-W Comparison
Detailed side-by-side comparison of EPC144LC20 by Intel and EPC1LC20-W by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC144LC20
EPC144LC20 - 144KB Serial Config PROM, 20-LCC | Intel (Altera)
EPC144LC20 β Last Time BuyAltera
EPC1LC20-W
EPC1LC20-W - 1Mb OTP Configuration PROM 20-PLCC | Intel/Altera
EPC1LC20-W ObsoleteSpecification Comparison
| Parameter | EPC144LC20 | EPC1LC20-W |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | Memory ICs |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $9.85 |
| Memory Capacity | 144 Kbit | β |
| Memory Organization | Serial (one-time programmable) | β |
| Interface Type | Altera Serial Configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | β |
| Programming Method | In-system via JTAG (IEEE 1149.1 / ByteBlaster / USB-Blaster) | β |
| Supply Voltage (VCC) | 3.0 V to 5.5 V | β |
| Operating Temperature | -40C to +85C (industrial) | β |
| Configuration Time (typical) | [DATA_NEEDED: configuration time at DCLK = 10 MHz] | β |
| Active Supply Current | [DATA_NEEDED: ICC active] | β |
| Standby Supply Current | [DATA_NEEDED: ICC standby] | β |
| Package | 20-pin LCC (Leadless Chip Carrier, JLCC-20) | 20-PLCC J-lead (9x9 mm) |
| Pin Count | 20 | β |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket or direct solder) |
| Supported FPGA Families | Altera FLEX 6000 / 8000 / 10K, ACEX 1K, MAX 3000 / 7000, APEX 20K | β |
| MSL Level | 3 (168 hours) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status per Intel PCN] | Compliant (Pb-free -W finish) |
| Lead-Free | Yes | β |
| Halogen-Free | [DATA_NEEDED] | β |
| JTAG Compliance | IEEE Std 1149.1 | β |
| Memory Type | β | OTP (One-Time Programmable) Configuration PROM |
| Memory Size | β | 1 Mbit |
| Configuration Clock (DCLK) | β | 8 MHz maximum |
| Supply Voltage | β | 3.3 V and 5.0 V |
| Interface | β | Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) |
| In-System Programming | β | Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V |
| Lead Finish | β | Pb-free (matte tin) - "-W" suffix |
| Daisy-Chain Support | β | Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs |
| Compression Support | β | Yes - stores compressed Altera FPGA bitstreams |
| Operating Temperature Range | β | [DATA_NEEDED: operating temperature range] |
| Programming Cycles | β | 1 (OTP) |
| Target FPGA Families | β | Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury |