EPC144LC20 vs EPC1LC20-W Vergleich
Detaillierter Direktvergleich von EPC144LC20 von Intel und EPC1LC20-W von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPC144LC20 - 144KB Serial Config PROM, 20-LCC | Intel (Altera)
EPC144LC20 ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EPC144LC20 | EPC1LC20-W |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | Memory ICs |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,10 | $9,85 |
| Memory Capacity | 144 Kbit | — |
| Memory Organization | Serial (one-time programmable) | — |
| Schnittstellentyp | Altera Serial Configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | — |
| Programming Method | In-system via JTAG (IEEE 1149.1 / ByteBlaster / USB-Blaster) | — |
| Supply Voltage (VCC) | 3.0 V to 5.5 V | — |
| Betriebstemperatur | -40C to +85C (industrial) | — |
| Configuration Time (typical) | [DATA_NEEDED: configuration time at DCLK = 10 MHz] | — |
| Active Supply Current | [DATA_NEEDED: ICC active] | — |
| Standby Supply Current | [DATA_NEEDED: ICC standby] | — |
| Gehäuse | 20-pin LCC (Leadless Chip Carrier, JLCC-20) | 20-PLCC J-lead (9x9 mm) |
| Pin-Anzahl | 20 | — |
| Montageart | Surface Mount | Surface Mount (PLCC socket or direct solder) |
| Supported FPGA Families | Altera FLEX 6000 / 8000 / 10K, ACEX 1K, MAX 3000 / 7000, APEX 20K | — |
| MSL-Level | 3 (168 hours) | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status per Intel PCN] | Compliant (Pb-free -W finish) |
| Lead-Free | Yes | — |
| Halogenfrei | [DATA_NEEDED] | — |
| JTAG Compliance | IEEE Std 1149.1 | — |
| Speichertyp | — | OTP (One-Time Programmable) Configuration PROM |
| Speichergröße | — | 1 Mbit |
| Configuration Clock (DCLK) | — | 8 MHz maximum |
| Versorgungsspannung | — | 3.3 V and 5.0 V |
| Schnittstelle | — | Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) |
| In-System Programming | — | Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V |
| Lead Finish | — | Pb-free (matte tin) - "-W" suffix |
| Daisy-Chain Support | — | Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs |
| Compression Support | — | Yes - stores compressed Altera FPGA bitstreams |
| Betriebstemperaturbereich | — | [DATA_NEEDED: operating temperature range] |
| Programming Cycles | — | 1 (OTP) |
| Target FPGA Families | — | Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury |