EPC144LC20 vs EPC1LC20-W Comparaison
Comparaison détaillée côte à côte de EPC144LC20 par Intel et EPC1LC20-W par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC144LC20 | EPC1LC20-W |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | Memory ICs |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,10 | $9,85 |
| Memory Capacity | 144 Kbit | — |
| Memory Organization | Serial (one-time programmable) | — |
| Type d'interface | Altera Serial Configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | — |
| Programming Method | In-system via JTAG (IEEE 1149.1 / ByteBlaster / USB-Blaster) | — |
| Supply Voltage (VCC) | 3.0 V to 5.5 V | — |
| Température de fonctionnement | -40C to +85C (industrial) | — |
| Configuration Time (typical) | [DATA_NEEDED: configuration time at DCLK = 10 MHz] | — |
| Active Supply Current | [DATA_NEEDED: ICC active] | — |
| Standby Supply Current | [DATA_NEEDED: ICC standby] | — |
| Boîtier | 20-pin LCC (Leadless Chip Carrier, JLCC-20) | 20-PLCC J-lead (9x9 mm) |
| Nombre de broches | 20 | — |
| Type de montage | Surface Mount | Surface Mount (PLCC socket or direct solder) |
| Supported FPGA Families | Altera FLEX 6000 / 8000 / 10K, ACEX 1K, MAX 3000 / 7000, APEX 20K | — |
| Niveau MSL | 3 (168 hours) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status per Intel PCN] | Compliant (Pb-free -W finish) |
| Lead-Free | Yes | — |
| Sans halogène | [DATA_NEEDED] | — |
| JTAG Compliance | IEEE Std 1149.1 | — |
| Type de mémoire | — | OTP (One-Time Programmable) Configuration PROM |
| Taille de mémoire | — | 1 Mbit |
| Configuration Clock (DCLK) | — | 8 MHz maximum |
| Tension d'alimentation | — | 3.3 V and 5.0 V |
| Interface | — | Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) |
| In-System Programming | — | Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V |
| Lead Finish | — | Pb-free (matte tin) - "-W" suffix |
| Daisy-Chain Support | — | Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs |
| Compression Support | — | Yes - stores compressed Altera FPGA bitstreams |
| Plage de température de fonctionnement | — | [DATA_NEEDED: operating temperature range] |
| Programming Cycles | — | 1 (OTP) |
| Target FPGA Families | — | Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury |