EPC144LC20 vs EPC1LC20-W Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC144LC20 sa pamamagitan ng Intel at EPC1LC20-W sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC144LC20 | EPC1LC20-W |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | Memory ICs |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Memory Capacity | 144 Kbit | — |
| Memory Organization | Serial (one-time programmable) | — |
| Uri ng Interface | Altera Serial Configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | — |
| Programming Method | In-system via JTAG (IEEE 1149.1 / ByteBlaster / USB-Blaster) | — |
| Supply Voltage (VCC) | 3.0 V to 5.5 V | — |
| Temperature na Operasyon | -40C to +85C (industrial) | — |
| Configuration Time (typical) | [DATA_NEEDED: configuration time at DCLK = 10 MHz] | — |
| Active Supply Current | [DATA_NEEDED: ICC active] | — |
| Standby Supply Current | [DATA_NEEDED: ICC standby] | — |
| Packhaging | 20-pin LCC (Leadless Chip Carrier, JLCC-20) | 20-PLCC J-lead (9x9 mm) |
| Bilang ng Pin | 20 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (PLCC socket or direct solder) |
| Supported FPGA Families | Altera FLEX 6000 / 8000 / 10K, ACEX 1K, MAX 3000 / 7000, APEX 20K | — |
| Level ng MSL | 3 (168 hours) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status per Intel PCN] | Compliant (Pb-free -W finish) |
| Lead-Free | Yes | — |
| Wala sa Halogen | [DATA_NEEDED] | — |
| JTAG Compliance | IEEE Std 1149.1 | — |
| Uri ng Memory | — | OTP (One-Time Programmable) Configuration PROM |
| Laki ng Memory | — | 1 Mbit |
| Configuration Clock (DCLK) | — | 8 MHz maximum |
| Volte ng Pagbibigay | — | 3.3 V and 5.0 V |
| Interface | — | Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) |
| In-System Programming | — | Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V |
| Lead Finish | — | Pb-free (matte tin) - "-W" suffix |
| Daisy-Chain Support | — | Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs |
| Compression Support | — | Yes - stores compressed Altera FPGA bitstreams |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Programming Cycles | — | 1 (OTP) |
| Target FPGA Families | — | Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury |