EPC160C100 vs EPC1213LC20 Comparison
Detailed side-by-side comparison of EPC160C100 by Altera and EPC1213LC20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPC160C100
EPC160C100 - Altera Enhanced Configuration Device | Intel FPGA
EPC160C100 ObsoleteSpecification Comparison
| Parameter | EPC160C100 | EPC1213LC20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | Memory ICs | EEPROM |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.20 | $7.40 |
| Device Type | Enhanced Configuration Device (EPC) for SRAM-based LUT FPGAs | β |
| Supported FPGA Families | Altera APEX, Cyclone, Stratix, and other SRAM-based LUT devices | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Configuration Density | 160 Mbit equivalent tier | β |
| Operating Voltage (Core) | 3.3 V | β |
| Programming Interface | JTAG (IEEE 1149.1) in-system programmable | β |
| Configuration Interface | Serial / Parallel, Altera nCONFIG/nSTATUS/CONF_DONE protocol | β |
| Package | PQFP-100 | 20-PLCC (J-lead, 9x9 mm) |
| Pin Count | 100 | β |
| Mounting Type | Surface Mount | Surface Mount |
| Cascade Support | Yes (nCASC pin for multi-FPGA daisy chain) | β |
| Memory Technology | Flash-based non-volatile configuration memory | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (Commercial) |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Memory Type | β | OTP Configuration PROM (Flash-based) |
| Memory Size | β | 212 Kbit |
| Interface | β | Serial (Altera FPGA configuration protocol) |
| Maximum Configuration Clock | β | 6 MHz |
| Supply Voltage (Core) | β | 5.0 V |
| I/O Voltage Tolerance | β | 3.3 V / 5.0 V |
| Programmability | β | One-Time Programmable (OTP) via IEEE 1149.1 JTAG |
| In-System Programmability | β | Yes (5.0 V and 3.3 V ISP) |
| Compression Support | β | Yes (FPGA decompresses bitstream during load) |
| Package Code | β | QCCJ |