EPC160C100 vs EPC1213LC20 Comparaison
Comparaison détaillée côte à côte de EPC160C100 par Altera et EPC1213LC20 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC160C100 | EPC1213LC20 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | Memory ICs | EEPROM |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $7,20 | $7,40 |
| Device Type | Enhanced Configuration Device (EPC) for SRAM-based LUT FPGAs | — |
| Supported FPGA Families | Altera APEX, Cyclone, Stratix, and other SRAM-based LUT devices | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Configuration Density | 160 Mbit equivalent tier | — |
| Operating Voltage (Core) | 3.3 V | — |
| Programming Interface | JTAG (IEEE 1149.1) in-system programmable | — |
| Configuration Interface | Serial / Parallel, Altera nCONFIG/nSTATUS/CONF_DONE protocol | — |
| Boîtier | PQFP-100 | 20-PLCC (J-lead, 9x9 mm) |
| Nombre de broches | 100 | — |
| Type de montage | Surface Mount | Surface Mount |
| Cascade Support | Yes (nCASC pin for multi-FPGA daisy chain) | — |
| Memory Technology | Flash-based non-volatile configuration memory | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0C to +70C (Commercial) |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Type de mémoire | — | OTP Configuration PROM (Flash-based) |
| Taille de mémoire | — | 212 Kbit |
| Interface | — | Serial (Altera FPGA configuration protocol) |
| Maximum Configuration Clock | — | 6 MHz |
| Supply Voltage (Core) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V / 5.0 V |
| Programmability | — | One-Time Programmable (OTP) via IEEE 1149.1 JTAG |
| In-System Programmability | — | Yes (5.0 V and 3.3 V ISP) |
| Compression Support | — | Yes (FPGA decompresses bitstream during load) |
| Package Code | — | QCCJ |