EPC160C100 vs EPC1213LC20 Vergleich
Detaillierter Direktvergleich von EPC160C100 von Altera und EPC1213LC20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC160C100 | EPC1213LC20 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | Memory ICs | EEPROM |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,20 | $7,40 |
| Device Type | Enhanced Configuration Device (EPC) for SRAM-based LUT FPGAs | — |
| Supported FPGA Families | Altera APEX, Cyclone, Stratix, and other SRAM-based LUT devices | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Configuration Density | 160 Mbit equivalent tier | — |
| Operating Voltage (Core) | 3.3 V | — |
| Programming Interface | JTAG (IEEE 1149.1) in-system programmable | — |
| Configuration Interface | Serial / Parallel, Altera nCONFIG/nSTATUS/CONF_DONE protocol | — |
| Gehäuse | PQFP-100 | 20-PLCC (J-lead, 9x9 mm) |
| Pin-Anzahl | 100 | — |
| Montageart | Surface Mount | Surface Mount |
| Cascade Support | Yes (nCASC pin for multi-FPGA daisy chain) | — |
| Memory Technology | Flash-based non-volatile configuration memory | — |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | 0C to +70C (Commercial) |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Speichertyp | — | OTP Configuration PROM (Flash-based) |
| Speichergröße | — | 212 Kbit |
| Schnittstelle | — | Serial (Altera FPGA configuration protocol) |
| Maximum Configuration Clock | — | 6 MHz |
| Supply Voltage (Core) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V / 5.0 V |
| Programmability | — | One-Time Programmable (OTP) via IEEE 1149.1 JTAG |
| In-System Programmability | — | Yes (5.0 V and 3.3 V ISP) |
| Compression Support | — | Yes (FPGA decompresses bitstream during load) |
| Package Code | — | QCCJ |