EPC160C100 vs EPC1213LC20 Comparación
Comparación detallada lado a lado de EPC160C100 por Altera y EPC1213LC20 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC160C100 | EPC1213LC20 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | Memory ICs | EEPROM |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,20 | $7,40 |
| Device Type | Enhanced Configuration Device (EPC) for SRAM-based LUT FPGAs | — |
| Supported FPGA Families | Altera APEX, Cyclone, Stratix, and other SRAM-based LUT devices | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Configuration Density | 160 Mbit equivalent tier | — |
| Operating Voltage (Core) | 3.3 V | — |
| Programming Interface | JTAG (IEEE 1149.1) in-system programmable | — |
| Configuration Interface | Serial / Parallel, Altera nCONFIG/nSTATUS/CONF_DONE protocol | — |
| Encapsulado | PQFP-100 | 20-PLCC (J-lead, 9x9 mm) |
| Recuento de pines | 100 | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Cascade Support | Yes (nCASC pin for multi-FPGA daisy chain) | — |
| Memory Technology | Flash-based non-volatile configuration memory | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0C to +70C (Commercial) |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Tipo de memoria | — | OTP Configuration PROM (Flash-based) |
| Tamaño de memoria | — | 212 Kbit |
| Interfaz | — | Serial (Altera FPGA configuration protocol) |
| Maximum Configuration Clock | — | 6 MHz |
| Supply Voltage (Core) | — | 5.0 V |
| I/O Voltage Tolerance | — | 3.3 V / 5.0 V |
| Programmability | — | One-Time Programmable (OTP) via IEEE 1149.1 JTAG |
| In-System Programmability | — | Yes (5.0 V and 3.3 V ISP) |
| Compression Support | — | Yes (FPGA decompresses bitstream during load) |
| Package Code | — | QCCJ |