EPC16QC-100T vs EPC16C100T Comparison

Detailed side-by-side comparison of EPC16QC-100T by Altera and EPC16C100T by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC16QC-100T EPC16C100T
Brand Altera Intel
Category Memory ICs FPGA & CPLD
Lifecycle Status Obsolete NRND
Memory Type Flash Configuration PROM (in-system programmable) —
Memory Density 16 Mbit (2 Mbyte) —
Supported FPGA Families Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K —
Configuration Data Width 8-bit or 16-bit (cascaded dual-device mode) —
Configuration Modes Serial (single device), Parallel (two cascaded devices) —
Data Compression Support Yes (35% to 55% bitstream reduction typical) —
JTAG / Boundary Scan IEEE 1149.1 compliant, in-system programmable —
Supply Voltage 3.3 V —
Package 100-pin PQFP (20 x 14 mm), 0.65 mm pitch 100-pin PQFP
Operating Temperature [DATA_NEEDED: Operating temperature range] -40C to +85C (industrial)
Cascade Interface nCE / nOE handshake for multi-device chains —
Programming Interface JTAG (IEEE 1149.1) and serial —
Endurance [DATA_NEEDED: Program/erase cycle rating] —
Data Retention [DATA_NEEDED: Data retention specification] —
RoHS Status unknown —
Lead-Free unknown —
MSL Level [DATA_NEEDED: Moisture sensitivity level] —
Mounting Type Surface Mount Surface Mount
Memory Size — 16 Mb
Device Type — Enhanced Configuration Device
Supported FPGAs — Stratix, Cyclone, APEX, Mercury (LUT-based)
Configuration Schemes — PS, PPS, FPP, PPA, JTAG
Interface — Serial / Parallel / JTAG (IEEE 1149.1)
Core Voltage — 3.3 V
I/O Voltage — 1.8 V to 3.3 V
Programmability — In-system via JTAG
Lead Pitch — 0.65 mm
Compression Support — Yes (Stratix / Stratix II)
Multi-Device Configuration — Yes (daisy chain)
Remote Update — Yes

Datasheets & Resources

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