EPC16QC-100T vs EPC16C100T 比較

詳細並排比較 EPC16QC-100T 由 Altera 與 EPC16C100T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC16QC-100T EPC16C100T
品牌 Altera Intel
類別 Memory ICs FPGA & CPLD
生命週期狀態 Obsolete NRND
記憶體類型 Flash Configuration PROM (in-system programmable) —
Memory Density 16 Mbit (2 Mbyte) —
Supported FPGA Families Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K —
Configuration Data Width 8-bit or 16-bit (cascaded dual-device mode) —
Configuration Modes Serial (single device), Parallel (two cascaded devices) —
Data Compression Support Yes (35% to 55% bitstream reduction typical) —
JTAG / Boundary Scan IEEE 1149.1 compliant, in-system programmable —
供應電壓 3.3 V —
封裝 100-pin PQFP (20 x 14 mm), 0.65 mm pitch 100-pin PQFP
工作溫度 [DATA_NEEDED: Operating temperature range] -40C to +85C (industrial)
Cascade Interface nCE / nOE handshake for multi-device chains —
Programming Interface JTAG (IEEE 1149.1) and serial —
Endurance [DATA_NEEDED: Program/erase cycle rating] —
Data Retention [DATA_NEEDED: Data retention specification] —
RoHS 狀態 unknown —
Lead-Free unknown —
MSL 等級 [DATA_NEEDED: Moisture sensitivity level] —
安裝類型 Surface Mount Surface Mount
記憶體容量 — 16 Mb
Device Type — Enhanced Configuration Device
Supported FPGAs — Stratix, Cyclone, APEX, Mercury (LUT-based)
Configuration Schemes — PS, PPS, FPP, PPA, JTAG
介面 — Serial / Parallel / JTAG (IEEE 1149.1)
Core Voltage — 3.3 V
I/O Voltage — 1.8 V to 3.3 V
Programmability — In-system via JTAG
Lead Pitch — 0.65 mm
Compression Support — Yes (Stratix / Stratix II)
Multi-Device Configuration — Yes (daisy chain)
Remote Update — Yes

資料表與資源

瀏覽所有產品 建立 BOM 索取報價