EPC2LI20 vs EPC2LI20J Comparison
Detailed side-by-side comparison of EPC2LI20 by Altera and EPC2LI20J by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2LI20 | EPC2LI20J |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.95 | $9.75 |
| Memory Size | 1.6 Mb (1,572,864 bits) | 1,695,680 bits (1.6Mb) |
| Memory Type | Flash (in-system programmable) | In-System Programmable Configuration PROM (flash) |
| Programmable Type | In System Programmable (ISP) | β |
| Function | Configuration PROM for SRAM-based FPGAs | β |
| Supply Voltage - Operating | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) | β |
| Operating Temperature | -40 C to +85 C (Industrial) | -40C to +85C (industrial) |
| Package / Case | 20-PLCC (J-lead, 9x9 mm) | β |
| Mounting Type | Surface Mount (PLCC socket-compatible) | β |
| Configuration Interface | Serial or Byte-wide (parallel) | β |
| Decompression | On-chip (supports compressed bitstreams) | β |
| JTAG / ISP Interface | IEEE 1532 (TCK, TMS, TDI, TDO) | β |
| Multi-Device Support | Yes (daisy-chain configuration) | β |
| User-Accessible Memory | Yes (unused flash available to user logic) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Organization | β | 65,536 x 1-bit (serial interface) |
| Interface | β | Altera 4-pin serial configuration (DATA, DCLK, nCS, nCONFIG) |
| Target FPGAs | β | APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA |
| Supply Voltage (VCCINT) | β | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Voltage (VCCIO) | β | 5.0 V or 3.3 V tolerant |
| ISP Programming Interface | β | JTAG (IEEE 1149.1) |
| Cascade Support | β | Yes (multi-device configuration chain) |
| Internal Oscillator | β | Yes (configures without external clock source) |
| Package | β | 20-pin PLCC with J-leads (JEDEC MS-018) |
| Programming Cycles | β | [DATA_NEEDED: minimum endurance cycles] |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| Configuration Clock (DCLK) | β | Up to 33 MHz |