EPC2LI20 vs EPC2LI20J 比較
詳細並排比較 EPC2LI20 由 Altera 與 EPC2LI20J 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2LI20 | EPC2LI20J |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | NRND | 啟用中 |
| 記憶體容量 | 1.6 Mb (1,572,864 bits) | 1,695,680 bits (1.6Mb) |
| 記憶體類型 | Flash (in-system programmable) | In-System Programmable Configuration PROM (flash) |
| Programmable Type | In System Programmable (ISP) | — |
| 功能 | Configuration PROM for SRAM-based FPGAs | — |
| Supply Voltage - Operating | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) | — |
| 工作溫度 | -40 C to +85 C (Industrial) | -40C to +85C (industrial) |
| 封裝 / 外殼 | 20-PLCC (J-lead, 9x9 mm) | — |
| 安裝類型 | Surface Mount (PLCC socket-compatible) | — |
| Configuration Interface | Serial or Byte-wide (parallel) | — |
| Decompression | On-chip (supports compressed bitstreams) | — |
| JTAG / ISP Interface | IEEE 1532 (TCK, TMS, TDI, TDO) | — |
| Multi-Device Support | Yes (daisy-chain configuration) | — |
| User-Accessible Memory | Yes (unused flash available to user logic) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| 組織 | — | 65,536 x 1-bit (serial interface) |
| 介面 | — | Altera 4-pin serial configuration (DATA, DCLK, nCS, nCONFIG) |
| Target FPGAs | — | APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Voltage (VCCIO) | — | 5.0 V or 3.3 V tolerant |
| ISP Programming Interface | — | JTAG (IEEE 1149.1) |
| Cascade Support | — | Yes (multi-device configuration chain) |
| Internal Oscillator | — | Yes (configures without external clock source) |
| 封裝 | — | 20-pin PLCC with J-leads (JEDEC MS-018) |
| Programming Cycles | — | [DATA_NEEDED: minimum endurance cycles] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Clock (DCLK) | — | Up to 33 MHz |