EPC2LI20 vs EPC2LI20J Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC2LI20 sa pamamagitan ng Altera at EPC2LI20J sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC2LI20 | EPC2LI20J |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | NRND | Aktibo |
| Laki ng Memory | 1.6 Mb (1,572,864 bits) | 1,695,680 bits (1.6Mb) |
| Uri ng Memory | Flash (in-system programmable) | In-System Programmable Configuration PROM (flash) |
| Programmable Type | In System Programmable (ISP) | — |
| Fungsi | Configuration PROM for SRAM-based FPGAs | — |
| Supply Voltage - Operating | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) | — |
| Temperature na Operasyon | -40 C to +85 C (Industrial) | -40C to +85C (industrial) |
| Packhaging / Kaso | 20-PLCC (J-lead, 9x9 mm) | — |
| Uri ng Pagpapasok | Surface Mount (PLCC socket-compatible) | — |
| Configuration Interface | Serial or Byte-wide (parallel) | — |
| Decompression | On-chip (supports compressed bitstreams) | — |
| JTAG / ISP Interface | IEEE 1532 (TCK, TMS, TDI, TDO) | — |
| Multi-Device Support | Yes (daisy-chain configuration) | — |
| User-Accessible Memory | Yes (unused flash available to user logic) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Organisasyon | — | 65,536 x 1-bit (serial interface) |
| Interface | — | Altera 4-pin serial configuration (DATA, DCLK, nCS, nCONFIG) |
| Target FPGAs | — | APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Voltage (VCCIO) | — | 5.0 V or 3.3 V tolerant |
| ISP Programming Interface | — | JTAG (IEEE 1149.1) |
| Cascade Support | — | Yes (multi-device configuration chain) |
| Internal Oscillator | — | Yes (configures without external clock source) |
| Packhaging | — | 20-pin PLCC with J-leads (JEDEC MS-018) |
| Programming Cycles | — | [DATA_NEEDED: minimum endurance cycles] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Clock (DCLK) | — | Up to 33 MHz |