EPC2LS20U vs EPC2LI20N Comparison
Detailed side-by-side comparison of EPC2LS20U by Altera and EPC2LI20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC2LS20U | EPC2LI20N |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.25 | $5.10 |
| Product Type | In-System Programmable Configuration PROM | β |
| Memory Density | 1.6 Mbit | β |
| Operating Voltage (VCC) | 3.3 V | β |
| Interface | Altera serial configuration / JTAG | β |
| Programming Method | In-System Programmable (ISP) via JTAG | β |
| Package | 20-PLCC (J-lead, 9x9 mm) | β |
| Lead-Free / RoHS | Yes (per "U" suffix) | β |
| Operating Temperature | [DATA_NEEDED: Operating Temperature] | [DATA_NEEDED: operating temperature range] |
| Supported FPGA Families | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 | β |
| Configuration Modes | PS (Passive Serial), AS, FPP | β |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | β |
| Done Pin | Yes (open-drain programmable polarity) | β |
| nSTATUS Pin | Yes (open-drain error flag) | β |
| nCONFIG Pin | Yes (reset/reconfiguration input) | β |
| DCLK Output | Yes (configuration clock to FPGA) | β |
| MSL Level | [DATA_NEEDED: MSL Level] | β |
| Compliance | RoHS (Pb-free per U suffix) | β |
| Memory Type | β | Non-volatile configuration PROM (Flash) |
| Memory Size | β | 1.6 Mbit |
| Programmable Type | β | In System Programmable (ISP via JTAG) |
| Configuration Mode | β | Serial |
| Maximum Configuration Frequency | β | 10 MHz |
| Supply Voltage (VCCINT) | β | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | β | 4.5 V to 5.5 V |
| Package / Case | β | 20-PLCC (J-Lead), 9x9 mm |
| Mounting Type | β | Surface Mount |
| Packaging | β | Tube |
| Supported FPGA Series | β | ACEX 1K, APEX II, Cyclone, Stratix II |
| JTAG Interface | β | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) |
| Configuration Pins | β | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |