EPC2LS20U vs EPC2LI20N Comparaison
Comparaison détaillée côte à côte de EPC2LS20U par Altera et EPC2LI20N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2LS20U | EPC2LI20N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $4,25 | $5,10 |
| Product Type | In-System Programmable Configuration PROM | — |
| Memory Density | 1.6 Mbit | — |
| Operating Voltage (VCC) | 3.3 V | — |
| Interface | Altera serial configuration / JTAG | — |
| Programming Method | In-System Programmable (ISP) via JTAG | — |
| Boîtier | 20-PLCC (J-lead, 9x9 mm) | — |
| Lead-Free / RoHS | Yes (per "U" suffix) | — |
| Température de fonctionnement | [DATA_NEEDED: Operating Temperature] | [DATA_NEEDED: operating temperature range] |
| Supported FPGA Families | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 | — |
| Configuration Modes | PS (Passive Serial), AS, FPP | — |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | — |
| Done Pin | Yes (open-drain programmable polarity) | — |
| nSTATUS Pin | Yes (open-drain error flag) | — |
| nCONFIG Pin | Yes (reset/reconfiguration input) | — |
| DCLK Output | Yes (configuration clock to FPGA) | — |
| Niveau MSL | [DATA_NEEDED: MSL Level] | — |
| Compliance | RoHS (Pb-free per U suffix) | — |
| Type de mémoire | — | Non-volatile configuration PROM (Flash) |
| Taille de mémoire | — | 1.6 Mbit |
| Programmable Type | — | In System Programmable (ISP via JTAG) |
| Configuration Mode | — | Serial |
| Maximum Configuration Frequency | — | 10 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | — | 4.5 V to 5.5 V |
| Boîtier / Format | — | 20-PLCC (J-Lead), 9x9 mm |
| Type de montage | — | Surface Mount |
| Packaging | — | Tube |
| Supported FPGA Series | — | ACEX 1K, APEX II, Cyclone, Stratix II |
| JTAG Interface | — | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) |
| Configuration Pins | — | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE |
| Statut RoHS | — | [DATA_NEEDED: RoHS status] |