EPC2LS20U vs EPC2LI20N Comparación
Comparación detallada lado a lado de EPC2LS20U por Altera y EPC2LI20N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2LS20U | EPC2LI20N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $4,25 | $5,10 |
| Product Type | In-System Programmable Configuration PROM | — |
| Memory Density | 1.6 Mbit | — |
| Operating Voltage (VCC) | 3.3 V | — |
| Interfaz | Altera serial configuration / JTAG | — |
| Programming Method | In-System Programmable (ISP) via JTAG | — |
| Encapsulado | 20-PLCC (J-lead, 9x9 mm) | — |
| Lead-Free / RoHS | Yes (per "U" suffix) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: Operating Temperature] | [DATA_NEEDED: operating temperature range] |
| Supported FPGA Families | Cyclone I/II, Stratix/II, APEX-II, ACEX-1K, FLEX-10K, FLEX-6000, MAX-7000 | — |
| Configuration Modes | PS (Passive Serial), AS, FPP | — |
| JTAG Support | Yes (IEEE 1149.1 boundary scan) | — |
| Done Pin | Yes (open-drain programmable polarity) | — |
| nSTATUS Pin | Yes (open-drain error flag) | — |
| nCONFIG Pin | Yes (reset/reconfiguration input) | — |
| DCLK Output | Yes (configuration clock to FPGA) | — |
| Nivel MSL | [DATA_NEEDED: MSL Level] | — |
| Compliance | RoHS (Pb-free per U suffix) | — |
| Tipo de memoria | — | Non-volatile configuration PROM (Flash) |
| Tamaño de memoria | — | 1.6 Mbit |
| Programmable Type | — | In System Programmable (ISP via JTAG) |
| Configuration Mode | — | Serial |
| Maximum Configuration Frequency | — | 10 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| Supply Voltage (VCCIO) | — | 4.5 V to 5.5 V |
| Encapsulado / Carcasa | — | 20-PLCC (J-Lead), 9x9 mm |
| Tipo de montaje | — | Surface Mount |
| Packaging | — | Tube |
| Supported FPGA Series | — | ACEX 1K, APEX II, Cyclone, Stratix II |
| JTAG Interface | — | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) |
| Configuration Pins | — | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE |
| Estado RoHS | — | [DATA_NEEDED: RoHS status] |