EPF8820ARC208-C vs EPF8820ARC208-3 Comparison
Detailed side-by-side comparison of EPF8820ARC208-C by Altera and EPF8820ARC208-3 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPF8820ARC208-3 - FLEX 8000 FPGA, 8K Gates, 672 Cells | Intel / Altera
EPF8820ARC208-3 ObsoleteSpecification Comparison
| Parameter | EPF8820ARC208-C | EPF8820ARC208-3 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $18.75 | $62.00 |
| Family | FLEX 8000 | FLEX 8000 (EPF8820) |
| Usable Gates | 8,000 | 8,000 |
| Logic Elements | 672 | β |
| Maximum User I/Os | 152 | β |
| Logic Array Blocks (LABs) | 8 to 16 LEs per LAB | β |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | β |
| I/O Voltage (VCCIO) | 3.3 V or 5.0 V (MultiVolt) | β |
| Process Technology | 0.42 um CMOS, 5 metal layers | 0.42 Β΅m CMOS |
| Configuration Technology | CMOS SRAM (volatile) | β |
| Operating Temperature | 0 C to +70 C (commercial) | β |
| Package | 208-RQFP Exposed Pad (28x28 mm, 0.5 mm pitch) | β |
| Mounting Type | Surface Mount | Surface Mount |
| In-Circuit Reconfigurability | Yes (ICR) | β |
| Boundary-Scan Support | Yes (IEEE 1149.1 JTAG) | β |
| Configuration Devices Supported | EPC1, EPC1213, EPC1064, EPC1441 | β |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| Series | β | FLEX 8000 |
| Logic Cells / Elements | β | 672 |
| Registers | β | 152 |
| Maximum Operating Frequency | β | 125 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V |
| Configuration Memory | β | SRAM (volatile) |
| Package / Case | β | 208-BFQFP Exposed Pad (208-RQFP, 28x28 mm) |
| Supplier Device Package | β | 208-RQFP (28x28) |
| Packaging | β | Tray |
| Operating Temperature Range | β | [DATA_NEEDED: operating temperature range] |
| In-Circuit Reconfigurability (ICR) | β | Yes (via external configuration devices) |
| Boundary-Scan Test | β | JTAG (IEEE 1149.1) |
| I/O Tolerance | β | 3.3 V / 5 V |
| Clock Networks | β | 4 dedicated low-skew global clocks |
| Lead-Free / Finish | β | [DATA_NEEDED: lead-free finish] |