EPM240T100C5 - MAX II CPLD, 192 Macrocells, 100-TQFP | Altera
MPN: EPM240T100C5 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $9.06 | $9.06 |
| 10 | $8.5 | $85.00 |
| 100 | $7.65 | $765.00 |
| 500 | $6.95 | $3,475.00 |
| 1,000 | $6.2 | $6,200.00 |
Drop-in alternatives for EPM240T100C5 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM240T100C5N
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View Datasheet βEPM240T100C5 Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 |
| Maximum User I/O Pins | 80 |
| Logic Elements | 240 |
| Non-volatile Memory | 8 Kbits (embedded Flash) |
| Pin-to-Pin Logic Delay (tPD1) | 4.7 ns |
| Maximum Internal Frequency | 201.1 MHz |
| Process Technology | 0.18 Β΅m, 6-layer metal Flash |
| Core Supply Voltage | 2.5 V / 3.3 V |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) |
| I/O Banks | 4 |
| Package | 100-pin TQFP (14 mm Γ 14 mm Γ 1 mm) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| Operating Temperature | 0C to +85C (Commercial) |
| Chip-wide Output Enable | DEV_OE pin |
EPM240T100C5 Pin Configuration
| Pin 1 | I/O β User I/O (Bank 1) |
| Pin 2 | I/O β User I/O (Bank 1) |
| Pin 3 | I/O β User I/O (Bank 1) |
| Pin 4 | I/O β User I/O (Bank 1) |
| Pin 5 | I/O β User I/O (Bank 1) |
| Pin 6 | VCCIO1 β Bank 1 I/O supply voltage |
| Pin 7 | I/O β User I/O (Bank 1) |
| Pin 8 | GND β Ground |
| Pin 9 | I/O β User I/O (Bank 1) |
| Pin 10 | I/O β User I/O (Bank 1) |
| Pin 11 | I/O β User I/O (Bank 1) |
| Pin 12 | I/O β User I/O (Bank 1) |
| Pin 13 | I/O β User I/O (Bank 1) |
| Pin 14 | I/O β User I/O (Bank 1) |
| Pin 15 | I/O β User I/O (Bank 1) |
| Pin 16 | VCCIO1 β Bank 1 I/O supply voltage |
| Pin 17 | I/O β User I/O (Bank 1) |
| Pin 18 | I/O β User I/O (Bank 1) |
| Pin 19 | I/O β User I/O (Bank 1) |
| Pin 20 | I/O β User I/O (Bank 1) |
| Pin 21 | I/O β User I/O (Bank 2) |
| Pin 22 | VCCIO2 β Bank 2 I/O supply voltage |
| Pin 23 | I/O β User I/O (Bank 2) |
| Pin 24 | GND β Ground |
| Pin 25 | I/O β User I/O (Bank 2) |
| Pin 26 | I/O β User I/O (Bank 2) |
| Pin 27 | I/O β User I/O (Bank 2) |
| Pin 28 | I/O β User I/O (Bank 2) |
| Pin 29 | I/O β User I/O (Bank 2) |
| Pin 30 | VCCIO2 β Bank 2 I/O supply voltage |
| Pin 31 | I/O β User I/O (Bank 2) |
| Pin 32 | I/O β User I/O (Bank 2) |
| Pin 33 | I/O β User I/O (Bank 2) |
| Pin 34 | I/O β User I/O (Bank 2) |
| Pin 35 | I/O β User I/O (Bank 2) |
| Pin 36 | I/O β User I/O (Bank 2) |
| Pin 37 | I/O β User I/O (Bank 2) |
| Pin 38 | VCCIO2 β Bank 2 I/O supply voltage |
| Pin 39 | I/O β User I/O (Bank 2) |
| Pin 40 | I/O β User I/O (Bank 2) |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O (Bank 3) |
| Pin 43 | I/O β User I/O (Bank 3) |
| Pin 44 | VCCIO3 β Bank 3 I/O supply voltage |
| Pin 45 | I/O β User I/O (Bank 3) |
| Pin 46 | I/O β User I/O (Bank 3) |
| Pin 47 | I/O β User I/O (Bank 3) |
| Pin 48 | I/O β User I/O (Bank 3) |
| Pin 49 | I/O β User I/O (Bank 3) |
| Pin 50 | VCCIO3 β Bank 3 I/O supply voltage |
| Pin 51 | I/O β User I/O (Bank 3) |
| Pin 52 | I/O β User I/O (Bank 3) |
| Pin 53 | I/O β User I/O (Bank 3) |
| Pin 54 | I/O β User I/O (Bank 3) |
| Pin 55 | I/O β User I/O (Bank 3) |
| Pin 56 | I/O β User I/O (Bank 3) |
| Pin 57 | VCCIO3 β Bank 3 I/O supply voltage |
| Pin 58 | I/O β User I/O (Bank 3) |
| Pin 59 | I/O β User I/O (Bank 3) |
| Pin 60 | I/O β User I/O (Bank 3) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O (Bank 4) |
| Pin 63 | I/O β User I/O (Bank 4) |
| Pin 64 | VCCIO4 β Bank 4 I/O supply voltage |
| Pin 65 | I/O β User I/O (Bank 4) |
| Pin 66 | I/O β User I/O (Bank 4) |
| Pin 67 | I/O β User I/O (Bank 4) |
| Pin 68 | I/O β User I/O (Bank 4) |
| Pin 69 | I/O β User I/O (Bank 4) |
| Pin 70 | VCCIO4 β Bank 4 I/O supply voltage |
| Pin 71 | I/O β User I/O (Bank 4) |
| Pin 72 | I/O β User I/O (Bank 4) |
| Pin 73 | I/O β User I/O (Bank 4) |
| Pin 74 | I/O β User I/O (Bank 4) |
| Pin 75 | I/O β User I/O (Bank 4) |
| Pin 76 | I/O β User I/O (Bank 4) |
| Pin 77 | VCCIO4 β Bank 4 I/O supply voltage |
| Pin 78 | I/O β User I/O (Bank 4) |
| Pin 79 | I/O β User I/O (Bank 4) |
| Pin 80 | I/O β User I/O (Bank 4) |
| Pin 81 | GND β Ground |
| Pin 82 | DEV_OE β Chip-wide output enable (active high) |
| Pin 83 | I/O β User I/O (Bank 4) |
| Pin 84 | I/O β User I/O (Bank 4) |
| Pin 85 | TDI β JTAG Test Data In |
| Pin 86 | TMS β JTAG Test Mode Select |
| Pin 87 | TCK β JTAG Test Clock |
| Pin 88 | TDO β JTAG Test Data Out |
| Pin 89 | VCCINT β Core supply voltage (2.5 V or 3.3 V) |
| Pin 90 | GND β Ground |
| Pin 91 | I/O β User I/O (Bank 1) |
| Pin 92 | I/O β User I/O (Bank 1) |
| Pin 93 | I/O β User I/O (Bank 1) |
| Pin 94 | I/O β User I/O (Bank 1) |
| Pin 95 | I/O β User I/O (Bank 1) |
| Pin 96 | VCCIO1 β Bank 1 I/O supply voltage |
| Pin 97 | I/O β User I/O (Bank 1) |
| Pin 98 | I/O β User I/O (Bank 1) |
| Pin 99 | I/O β User I/O (Bank 1) |
| Pin 100 | I/O β User I/O (Bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM240T100C5 is suitable for 6 applications: Microcontroller I/O Expansion and Glue Logic, Power Supply Sequencing in Multi-Rail Systems, FPGA Configuration and Boot Control, Bus Interface Bridging (LVCMOS, LVTTL, PCI), Industrial Automation Control Logic, Address Decoding in Memory Subsystems.
Microcontroller I/O Expansion and Glue Logic
The EPM240T100C5 expands a host MCU's limited GPIO by decoding address lines and generating chip-select strobes for peripherals like SRAM, Flash, and sensors. Its 192 macrocells and 80 user I/O pins provide ample headroom for 8-bit and 16-bit bus decoding, while the 4.7 ns pin-to-pin delay ensures address-to-CS propagation stays well under one 50 MHz system clock period. The instant-on non-volatile Flash eliminates boot-PROM overhead, so the CPLD is ready to drive chip-selects before the MCU finishes its PLL lock - critical for deterministic power-on behavior. Designers typically place the CPLD between the MCU EMI bus and 4-8 peripheral devices, freeing the MCU's GPIO for serial interfaces.
Recommended
Power Supply Sequencing in Multi-Rail Systems
The EPM240T100C5 sequences 3-6 voltage rails (1.0 V core, 1.5 V DDR, 1.8 V I/O, 2.5 V PLLs, 3.3 V analog) in the correct order during power-up and reverse order during power-down. Each macrocell implements a comparator-and-counter state machine that watches a PGOOD signal and asserts the next rail's enable after a configurable delay. The non-volatile Flash means the sequencing logic is active within microseconds of VCCINT reaching 2.5 V, eliminating the race condition between bulk-capacitor charging and rail-monitors. Designers typically route 4 power-good inputs to the CPLD and 6 enable outputs to DC-DC converter PG pins.
Recommended
FPGA Configuration and Boot Control
The EPM240T100C5 acts as a configuration controller for SRAM-based FPGAs that require multi-mode boot (JTAG / parallel / serial). It reads the FPGA's configuration mode-pins and drives them based on a user-defined mode sequence, holds the FPGA in RESET until VCCINT is stable, and generates the PROG_B pulse on demand. The 8 Kbit embedded Flash stores the mode-selection logic permanently, so no external PROM is needed. Designers route DONE, INIT_B, and CONFIG_B lines from the FPGA to the CPLD, with the CPLD returning CTRL0/CTRL1 selections. This pattern is common in industrial and telecom designs where field-upgrade flexibility is required.
Recommended
Bus Interface Bridging (LVCMOS, LVTTL, PCI)
The EPM240T100C5 bridges between mismatched bus standards - for example, translating a 3.3 V LVCMOS microcontroller bus to 1.8 V LVCMOS peripherals or providing a 5-V-tolerant input buffer for legacy PCI signals (when VCCIO is set to 3.3 V). Four I/O banks allow voltage-domain isolation so 1.5 V, 1.8 V, 2.5 V, and 3.3 V devices can all connect to the same CPLD without external level-shifters. With 4.7 ns tPD, the bridge introduces negligible latency into memory-mapped interfaces. Typical designs use 8-16 macrocells per 8-bit bus-converter instance, leaving headroom for handshaking and parity logic.
Recommended
Industrial Automation Control Logic
In factory-automation PLCs, distributed I/O blocks, and motor-control auxiliary boards, the EPM240T100C5 implements deterministic state machines for safety-interlock logic, encoder-decoder counting, and PWM-edge multiplexing. Its 0-85C commercial or -40-85C industrial variants and 4.7 ns tPD suit real-time control loops. The on-chip pull-up resistors (configurable per User I/O pin 4) reduce BOM cost by eliminating external 10K arrays. Designers typically deploy 1-2 CPLDs per PLC chassis to consolidate discrete logic that would otherwise require dozens of 74HC-series gates.
Recommended
Address Decoding in Memory Subsystems
The EPM240T100C5 decodes 24-32 bit address lines into individual chip-selects for Flash, SRAM, DRAM, and peripheral registers in embedded systems. A typical implementation uses 32 macrocells to generate 8 chip-selects with address-range masking via internal feedback comparators. The instant-on behavior ensures the chip-selects are valid at the first clock edge after reset, eliminating the boot-window violation that occurs with SRAM-based FPGAs. Designers often combine this application with bus-cycle termination logic (RDY/BWAIT stretching) using the same CPLD, saving board area versus discrete MSI logic.
Recommended
Recommended Products Summary
Engineering reference data for EPM240T100C5 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM240T100C5N | EPM240T100C4N | EPM240T100C4 | EPM240T100C3N | EPM240GT100C5N | EPM240GT100C5 |
|---|---|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Family | MAX II | MAX II | MAX II | MAX II | MAX II | MAX II G | MAX II G |
| Speed Grade | C5 (4.7 ns tPD) | C5 (4.7 ns tPD) | C4 (slower tPD) | C4 (slower tPD) | C3 (slowest tPD) | C5 | C5 |
| Lead-Free (RoHS) | No (leaded) | Yes (Pb-free) | Yes (Pb-free) | No (leaded) | Yes (Pb-free) | Yes (Pb-free) | No (leaded) |
| Macrocells | 192 | 192 | 192 | 192 | 192 | 192 | 192 |
| Non-volatile Flash | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits |
| Core Voltage | 2.5 V / 3.3 V | 2.5 V / 3.3 V | 2.5 V / 3.3 V | 2.5 V / 3.3 V | 2.5 V / 3.3 V | 1.8 V / 2.5 V / 3.3 V | 1.8 V / 2.5 V / 3.3 V |
Key Differentiators
- Faster speed grade than C4/C3 alternatives at identical footprint (vs EPM240T100C4N)
- Lower unit cost than MAX II G family with identical macrocell count (vs EPM240GT100C5N)
- Leaded (SnPb) finish for legacy / non-RoHS assembly (vs EPM240T100C5N)
Design Notes
Decouple each VCCINT and VCCIO pin with a 0.1 Β΅F ceramic capacitor placed within 5 mm of the respective pin and a 10 Β΅F bulk tantalum or ceramic capacitor at the board-level supply rail. The four VCCIO banks allow mixed-voltage operation (1.5 V / 1.8 V / 2.5 V / 3.3 V) but each bank must share a common voltage; do not drive signals between different VCCIO domains without series resistors or level shifters if voltage mismatch exceeds 0.3 V.
The 100-pin TQFP has a 0.5 mm pitch and 14 mm Γ 14 mm body - use 4-mil (0.1 mm) traces between pads with 8-mil (0.2 mm) clearance for escape routing. Place a continuous ground plane on the layer directly beneath the device to minimize ground bounce on the JTAG and DEV_OE pins. Route JTAG signals (TDI, TMS, TCK, TDO) in a daisy-chain with 10K pull-ups on TDI/TMS/TCK as recommended in the MAX II handbook.
When using the EPM240T100C5 for high-speed address decoding or bus-bridging, observe 50 ohm controlled-impedance routing on outputs driving more than 25 mm of trace. Source-synchronous clocks should be assigned to dedicated clock input pins and use the on-chip PLL-free global clock network - the MAX II does not contain a PLL, so clock multiplication must be implemented in the macrocell fabric. Add 22-33 ohm series damping resistors on outputs driving backplane connectors to suppress ringing.
Do not apply 5.0 V to any I/O pin when VCCIO is set to less than 3.3 V - the absolute-maximum VCCIO+0.3 V input rating applies, and 5 V tolerance requires VCCIO = 3.3 V. Do not leave JTAG pins floating during in-system operation; floating TMS or TCK can inadvertently trigger boundary-scan operations. Verify that the Quartus II .pof programming file matches the target device ID before JTAG programming - using a C5 image on a C4 device will fail verification.
Compliance Information
EPM240T100C5 is leaded (SnPb finish) and not RoHS compliant. For RoHS-compliant production, use the EPM240T100C5N variant. AEC-Q100 qualification does not apply (commercial temperature range 0-85C). Industrial -40-85C variant is EPM240T100I5N.
