EPM240GT100I5N vs EPM240T100C5 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240GT100I5N sa pamamagitan ng Altera at EPM240T100C5 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM240GT100I5N | EPM240T100C5 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Katayuan ng Stock | — | In Stock |
| Presyo ng Yunit (USD) | — | $4.92 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX II | MAX II |
| Logic Elements (LEs) | 240 | — |
| Equivalent Macrocells | 192 | — |
| User I/Os | 80 | — |
| Propagation Delay (tPD) | 4.7 ns | — |
| Internal Performance (fMAX) | 304 MHz | — |
| Embedded Non-Volatile Memory | 8 Kbits user Flash | — |
| Process Technology | 0.18 µm 6-layer-metal Flash CMOS | 0.18 µm, 6-layer metal Flash |
| Supply Voltage - Core (VCCINT) | 1.71 V to 1.89 V (3.3 V tolerant for MAX II G variant) | — |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V MultiVolt I/O | — |
| Programming Interface | JTAG (IEEE 1149.1) ISP | JTAG (IEEE 1149.1) / ISP |
| Packhaging | 100-pin TQFP (14x14 mm, 0.5 mm pitch) | 100-pin TQFP (14 mm × 14 mm × 1 mm) |
| Temperature na Operasyon | -40 °C to +100 °C (Industrial) | 0C to +85C (Commercial) |
| Lead-Free / RoHS | Yes (suffix N) | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 192 |
| Maximum User I/O Pins | — | 80 |
| Logic Elements | — | 240 |
| Non-volatile Memory | — | 8 Kbits (embedded Flash) |
| Pin-to-Pin Logic Delay (tPD1) | — | 4.7 ns |
| Maximum Internal Frequency | — | 201.1 MHz |
| Core Supply Voltage | — | 2.5 V / 3.3 V |
| I/O Voltage Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) |
| I/O Banks | — | 4 |
| Chip-wide Output Enable | — | DEV_OE pin |