EPM3064ATC100-4 vs EPM3064ATC100-10 Comparison

Detailed side-by-side comparison of EPM3064ATC100-4 by Altera and EPM3064ATC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM3064ATC100-4

EPM3064ATC100-4 - 64-Macrocell CPLD, 4.5ns, 100-TQFP | Altera

EPM3064ATC100-4 Nrnd

Specification Comparison

Parameter EPM3064ATC100-4 EPM3064ATC100-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $5.20 $2.85
Family MAX 3000A MAX 3000A
Device Type CPLD (EEPROM-based) β€”
Macro Cells 64 β€”
Logic Array Blocks (LABs) 2 β€”
Usable Gates 1,250 (range 600 to 10,000 across family) β€”
Maximum User I/O Pins 34 β€”
Pin-to-Pin Delay (tPD) 4.5 ns β€”
Counter Frequency (fCNT) 227.3 MHz β€”
Internal Performance 222.2 MHz β€”
Supply Voltage VCCINT 3.3 V β€”
I/O Voltage (MultiVolt) 2.5 V / 3.3 V / 5.0 V β€”
In-System Programming Yes (IEEE 1149.1 JTAG) β€”
Process Technology CMOS EEPROM CMOS EEPROM
Package 100-pin TQFP TQFP-100 (100-pin Thin Quad Flat Pack)
Mounting Type Surface Mount β€”
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: industrial temp grade option] β€”
RoHS Status unknown [DATA_NEEDED: RoHS compliance]
Architecture 5-level Altera MAX β€”
Logic Gates β€” 1250 gates
Macrocells β€” 64
Logic Array Blocks β€” 2
User I/O Pins β€” 34
Propagation Delay (tPD) β€” 10 ns
Supply Voltage (VCCINT) β€” 3.3 V
In-System Programmability β€” IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant
Global Clock Signals β€” 2 (with optional inversion)
Output Enable Signals β€” 6 or 10 pin- or logic-driven
Output Slew-Rate Control β€” Programmable
Operating Temperature Grade β€” Commercial
MultiVolt I/O Support β€” 1.5V / 1.8V / 2.5V / 3.3V interfaces

Datasheets & Resources

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