EPM3064ATC100-4 vs EPM3064ATC100-10 比較
詳細な並列比較: EPM3064ATC100-4 メーカー: Altera および EPM3064ATC100-10 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM3064ATC100-10 - 64-Macrocell MAX 3000A CPLD, 100MHz, TQFP-100 | Altera
EPM3064ATC100-10 Nrnd仕様比較
| パラメータ | EPM3064ATC100-4 | EPM3064ATC100-10 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $5.20 | $2.85 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (EEPROM-based) | — |
| Macro Cells | 64 | — |
| Logic Array Blocks (LABs) | 2 | — |
| Usable Gates | 1,250 (range 600 to 10,000 across family) | — |
| Maximum User I/O Pins | 34 | — |
| Pin-to-Pin Delay (tPD) | 4.5 ns | — |
| Counter Frequency (fCNT) | 227.3 MHz | — |
| Internal Performance | 222.2 MHz | — |
| Supply Voltage VCCINT | 3.3 V | — |
| I/O Voltage (MultiVolt) | 2.5 V / 3.3 V / 5.0 V | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| パッケージ | 100-pin TQFP | TQFP-100 (100-pin Thin Quad Flat Pack) |
| 実装タイプ | Surface Mount | — |
| 動作温度 | 0C to +70C (commercial) [DATA_NEEDED: industrial temp grade option] | — |
| RoHS ステータス | unknown | [DATA_NEEDED: RoHS compliance] |
| Architecture | 5-level Altera MAX | — |
| Logic Gates | — | 1250 gates |
| Macrocells | — | 64 |
| Logic Array Blocks | — | 2 |
| User I/O Pins | — | 34 |
| Propagation Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT) | — | 3.3 V |
| In-System Programmability | — | IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant |
| Global Clock Signals | — | 2 (with optional inversion) |
| Output Enable Signals | — | 6 or 10 pin- or logic-driven |
| Output Slew-Rate Control | — | Programmable |
| Operating Temperature Grade | — | Commercial |
| MultiVolt I/O Support | — | 1.5V / 1.8V / 2.5V / 3.3V interfaces |