EPM3064ATC100-4 vs EPM3064ATC100-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC100-4 sa pamamagitan ng Altera at EPM3064ATC100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATC100-4 EPM3064ATC100-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND NRND
Family MAX 3000A MAX 3000A
Device Type CPLD (EEPROM-based) —
Macro Cells 64 —
Logic Array Blocks (LABs) 2 —
Usable Gates 1,250 (range 600 to 10,000 across family) —
Maximum User I/O Pins 34 —
Pin-to-Pin Delay (tPD) 4.5 ns —
Counter Frequency (fCNT) 227.3 MHz —
Internal Performance 222.2 MHz —
Supply Voltage VCCINT 3.3 V —
I/O Voltage (MultiVolt) 2.5 V / 3.3 V / 5.0 V —
In-System Programming Yes (IEEE 1149.1 JTAG) —
Process Technology CMOS EEPROM CMOS EEPROM
Packhaging 100-pin TQFP TQFP-100 (100-pin Thin Quad Flat Pack)
Uri ng Pagpapasok Surface Mount —
Temperature na Operasyon 0C to +70C (commercial) [DATA_NEEDED: industrial temp grade option] —
Tindminan RoHS unknown [DATA_NEEDED: RoHS compliance]
Architecture 5-level Altera MAX —
Logic Gates — 1250 gates
Macrocells — 64
Logic Array Blocks — 2
User I/O Pins — 34
Propagation Delay (tPD) — 10 ns
Supply Voltage (VCCINT) — 3.3 V
In-System Programmability — IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant
Global Clock Signals — 2 (with optional inversion)
Output Enable Signals — 6 or 10 pin- or logic-driven
Output Slew-Rate Control — Programmable
Operating Temperature Grade — Commercial
MultiVolt I/O Support — 1.5V / 1.8V / 2.5V / 3.3V interfaces

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