EPM3064ATC100-4N vs EPM3064ATC100-4 Comparison
Detailed side-by-side comparison of EPM3064ATC100-4N by Altera and EPM3064ATC100-4 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3064ATC100-4N
EPM3064ATC100-4N - MAX 3000A CPLD, 64 Macro, 66 I/O, 100-TQFP
EPM3064ATC100-4N NrndAltera
EPM3064ATC100-4
EPM3064ATC100-4 - 64-Macrocell CPLD, 4.5ns, 100-TQFP | Altera
EPM3064ATC100-4 NrndSpecification Comparison
| Parameter | EPM3064ATC100-4N | EPM3064ATC100-4 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.60 | $5.20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (EEPROM-based) |
| Macro Cells | 64 | 64 |
| Logic Array Blocks | 2 | β |
| Usable Gates | 1,250 | 1,250 (range 600 to 10,000 across family) |
| User I/O Pins | 66 | β |
| Pin-to-Pin Delay (tPD) | 4.5 ns | 4.5 ns |
| Counter Frequency | 222.2 MHz (max) | β |
| Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | β |
| Package | 100-pin TQFP | 100-pin TQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | β |
| ISP Standard | IEEE Std. 1532 | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: industrial temp grade option] |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown |
| Logic Array Blocks (LABs) | β | 2 |
| Maximum User I/O Pins | β | 34 |
| Counter Frequency (fCNT) | β | 227.3 MHz |
| Internal Performance | β | 222.2 MHz |
| Supply Voltage VCCINT | β | 3.3 V |
| I/O Voltage (MultiVolt) | β | 2.5 V / 3.3 V / 5.0 V |
| In-System Programming | β | Yes (IEEE 1149.1 JTAG) |
| Architecture | β | 5-level Altera MAX |