EPM3064ATC100-4N vs EPM3064ATC100-4 Vergleich
Detaillierter Direktvergleich von EPM3064ATC100-4N von Altera und EPM3064ATC100-4 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3064ATC100-4N | EPM3064ATC100-4 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,60 | $5,20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (EEPROM-based) |
| Macro Cells | 64 | 64 |
| Logic Array Blocks | 2 | — |
| Usable Gates | 1,250 | 1,250 (range 600 to 10,000 across family) |
| User I/O Pins | 66 | — |
| Pin-to-Pin Delay (tPD) | 4.5 ns | 4.5 ns |
| Counter Frequency | 222.2 MHz (max) | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| Gehäuse | 100-pin TQFP | 100-pin TQFP |
| Montageart | Surface Mount | Surface Mount |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | — |
| ISP Standard | IEEE Std. 1532 | — |
| Betriebstemperatur | 0C to +70C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: industrial temp grade option] |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| RoHS-Status | [DATA_NEEDED: RoHS status] | unknown |
| Logic Array Blocks (LABs) | — | 2 |
| Maximum User I/O Pins | — | 34 |
| Counter Frequency (fCNT) | — | 227.3 MHz |
| Internal Performance | — | 222.2 MHz |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Voltage (MultiVolt) | — | 2.5 V / 3.3 V / 5.0 V |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Architecture | — | 5-level Altera MAX |