EPM3064ATC100-4N vs EPM3064ATC100-4 对比
详细并排对比 EPM3064ATC100-4N 出自 Altera 和 EPM3064ATC100-4 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM3064ATC100-4N | EPM3064ATC100-4 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 不推荐新设计 | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $4.60 | $5.20 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (EEPROM-based) |
| Macro Cells | 64 | 64 |
| Logic Array Blocks | 2 | — |
| Usable Gates | 1,250 | 1,250 (range 600 to 10,000 across family) |
| User I/O Pins | 66 | — |
| Pin-to-Pin Delay (tPD) | 4.5 ns | 4.5 ns |
| Counter Frequency | 222.2 MHz (max) | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| 封装 | 100-pin TQFP | 100-pin TQFP |
| 安装类型 | Surface Mount | Surface Mount |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | — |
| ISP Standard | IEEE Std. 1532 | — |
| 工作温度 | 0C to +70C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: industrial temp grade option] |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | unknown |
| Logic Array Blocks (LABs) | — | 2 |
| Maximum User I/O Pins | — | 34 |
| Counter Frequency (fCNT) | — | 227.3 MHz |
| Internal Performance | — | 222.2 MHz |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Voltage (MultiVolt) | — | 2.5 V / 3.3 V / 5.0 V |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Architecture | — | 5-level Altera MAX |