EPM3064ATI44-10N vs EPM3064ATI44-10 Comparison
Detailed side-by-side comparison of EPM3064ATI44-10N by Altera and EPM3064ATI44-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3064ATI44-10N | EPM3064ATI44-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3.95 | $7.65 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | β |
| Usable Gates | 1250 | β |
| User I/Os | 34 | β |
| Dedicated Inputs | 4 | β |
| Logic Blocks | 4 | β |
| Pin-to-Pin Delay | 10 ns (-10 speed grade) | β |
| Maximum Frequency (fMAX) | 100 MHz | β |
| Programmable Type | In-System Programmable (EEPROM) | In-System Programmable (ISP), EEPROM-based |
| ISP Interface | IEEE Std. 1149.1 (JTAG) | β |
| ISP Standard Compliance | IEEE Std. 1532 | β |
| Core Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V (MultiVolt) | β |
| Operating Temperature | -40C to +85C (Industrial, "N" suffix) | -40C to +85C (Industrial) |
| Package | 44-pin TQFP | TQFP-44 (10x10 mm, 0.8 mm pitch) |
| Process Technology | CMOS EEPROM | CMOS, EEPROM |
| Boundary-Scan Test | Built-in (JTAG) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Lead-Free Status | Contains Lead (per digchip datasheet excerpt) | β |
| RoHS Status | Non-Compliant (per digchip datasheet excerpt) | Non-Compliant (contains lead, per DigiChip listing) |
| Number of Macrocells | β | 64 |
| Number of Logic Array Blocks (LABs) | β | 4 |
| Number of Usable Gates | β | 1,250 |
| Number of User I/O Pins | β | 34 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Maximum Counter Frequency | β | 227.3 MHz |
| Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Voltage Tolerance | β | 5.0 V tolerant (MultiVolt I/O) |
| JTAG Interface | β | IEEE Std. 1149.1 compliant |
| ISP Standard | β | IEEE Std. 1532 |
| Lead Free Status | β | Contains Lead |
| Programming Cycles | β | [DATA_NEEDED: typical program/erase endurance] |