EPM3064ATI44-10N vs EPM3064ATI44-10 비교

다음의 상세 나란히 비교: EPM3064ATI44-10N 제조: Altera 및 EPM3064ATI44-10 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM3064ATI44-10N EPM3064ATI44-10
브랜드 Altera Intel
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete NRND
재고 상태 In Stock In Stock
단가 (USD) $3.95 $7.65
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 64 —
Usable Gates 1250 —
User I/Os 34 —
Dedicated Inputs 4 —
Logic Blocks 4 —
Pin-to-Pin Delay 10 ns (-10 speed grade) —
Maximum Frequency (fMAX) 100 MHz —
Programmable Type In-System Programmable (EEPROM) In-System Programmable (ISP), EEPROM-based
ISP Interface IEEE Std. 1149.1 (JTAG) —
ISP Standard Compliance IEEE Std. 1532 —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V (MultiVolt) —
동작 온도 -40C to +85C (Industrial, "N" suffix) -40C to +85C (Industrial)
패키지 44-pin TQFP TQFP-44 (10x10 mm, 0.8 mm pitch)
Process Technology CMOS EEPROM CMOS, EEPROM
Boundary-Scan Test Built-in (JTAG) —
실장 유형 Surface Mount Surface Mount
Lead-Free Status Contains Lead (per digchip datasheet excerpt) —
RoHS 상태 Non-Compliant (per digchip datasheet excerpt) Non-Compliant (contains lead, per DigiChip listing)
Number of Macrocells — 64
Number of Logic Array Blocks (LABs) — 4
Number of Usable Gates — 1,250
Number of User I/O Pins — 34
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Counter Frequency — 227.3 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Voltage Tolerance — 5.0 V tolerant (MultiVolt I/O)
JTAG Interface — IEEE Std. 1149.1 compliant
ISP Standard — IEEE Std. 1532
Lead Free Status — Contains Lead
Programming Cycles — [DATA_NEEDED: typical program/erase endurance]

데이터시트 & 자료

모든 제품 보기 BOM 생성 견적 요청