EPM3064ATI44-10N vs EPM3064ATI44-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATI44-10N sa pamamagitan ng Altera at EPM3064ATI44-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3064ATI44-10N | EPM3064ATI44-10 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 64 | — |
| Usable Gates | 1250 | — |
| User I/Os | 34 | — |
| Dedicated Inputs | 4 | — |
| Logic Blocks | 4 | — |
| Pin-to-Pin Delay | 10 ns (-10 speed grade) | — |
| Maximum Frequency (fMAX) | 100 MHz | — |
| Programmable Type | In-System Programmable (EEPROM) | In-System Programmable (ISP), EEPROM-based |
| ISP Interface | IEEE Std. 1149.1 (JTAG) | — |
| ISP Standard Compliance | IEEE Std. 1532 | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V (MultiVolt) | — |
| Temperature na Operasyon | -40C to +85C (Industrial, "N" suffix) | -40C to +85C (Industrial) |
| Packhaging | 44-pin TQFP | TQFP-44 (10x10 mm, 0.8 mm pitch) |
| Process Technology | CMOS EEPROM | CMOS, EEPROM |
| Boundary-Scan Test | Built-in (JTAG) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Lead-Free Status | Contains Lead (per digchip datasheet excerpt) | — |
| Tindminan RoHS | Non-Compliant (per digchip datasheet excerpt) | Non-Compliant (contains lead, per DigiChip listing) |
| Number of Macrocells | — | 64 |
| Number of Logic Array Blocks (LABs) | — | 4 |
| Number of Usable Gates | — | 1,250 |
| Number of User I/O Pins | — | 34 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5.0 V tolerant (MultiVolt I/O) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| ISP Standard | — | IEEE Std. 1532 |
| Lead Free Status | — | Contains Lead |
| Programming Cycles | — | [DATA_NEEDED: typical program/erase endurance] |