EPM3128ATC100-10 vs EPM3128ATC100-10NS Comparison

Detailed side-by-side comparison of EPM3128ATC100-10 by Altera and EPM3128ATC100-10NS by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3128ATC100-10 EPM3128ATC100-10NS
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $8.10 $6.50
Device Family MAX 3000A β€”
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 128 β€”
User I/Os 80 80
Usable Gates 2500 β€”
Propagation Delay (tPD) 10 ns β€”
Counter Frequency 227.3 MHz β€”
Supply Voltage (VCCINT) 3.3 V β€”
I/O Voltage Tolerance 5.0 V / 3.3 V / 2.5 V (MultiVolt) β€”
Package 100-pin TQFP TQFP-100
Mounting Type Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
In-System Programming IEEE Std. 1532 compliant (JTAG) β€”
PCI Compliance PCI Local Bus Specification Rev 2.2 (selected speed grades) β€”
Logic Family CMOS β€”
Operating Temperature 0 C to 70 C (commercial) [DATA_NEEDED: operating temperature range]
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Family β€” MAX 3000A
Macro Cells β€” 128
Pin Count β€” 100
Pin-to-Pin Logic Delay (tPD) β€” 10 ns
Counter Frequency (fCNT) β€” up to 227.3 MHz
Supply Voltage - Core (VCCINT) β€” 3.3 V
Supply Voltage - I/O (VCCIO) β€” 3.3 V or 2.5 V (5.0 V-tolerant inputs)
Logic-Level Compatibility β€” 5.0 V, 3.3 V, 2.5 V
Programmability β€” In-system (ISP), IEEE Std. 1532
Boundary Scan β€” IEEE 1149.1 JTAG
Lead-Free β€” [DATA_NEEDED: lead-free status]

Datasheets & Resources

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