EPM3128ATC100-10N vs EPM3128ATC100-5 Comparison

Detailed side-by-side comparison of EPM3128ATC100-10N by Altera and EPM3128ATC100-5 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3128ATC100-10N EPM3128ATC100-5
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Family MAX 3000A CPLD - MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Macro Cells 128 —
Usable Gates 2500 2,500
Number of I/O 80 —
Logic Elements / Blocks 8 LABs (16 macrocells each) —
Propagation Delay (tPD) 10 ns —
Maximum Internal Frequency (fMAX) 98 MHz —
Supply Voltage VCCINT 3.3 V —
I/O Bank Voltage VCCIO 3.3 V or 2.5 V (selectable) —
Configuration Memory CMOS EEPROM (non-volatile, instant-on) —
In-System Programming IEEE Std. 1532-compliant ISP via JTAG —
Package 100-pin TQFP (14 x 14 x 1.0 mm) 100-pin TQFP (Fine Line)
Operating Temperature 0 °C to +70 °C (commercial) 0 °C to 70 °C (Commercial)
Mounting Type Surface Mount Surface Mount
RoHS Status Compliant [DATA_NEEDED: RoHS status]
Lead-Free Yes —
MSL Level 3 (per JEDEC J-STD-020) —
Series — MAX 3000A
Macrocells — 128
User I/Os — 80
Dedicated Inputs — 4
Pin-to-Pin Delay (tpd) — 5 ns (commercial); 7.5 ns
Maximum Frequency (fCNT) — 192.3 MHz
Supply Voltage (VCCINT/VCCIO) — 3.3 V
Output Drive Voltage — 2.5 V or 3.3 V (programmable)
Input Tolerance — 2.5 V, 3.3 V, 5.0 V tolerant
Program Memory Type — EEPROM
In-System Programmability — Yes, IEEE Std. 1532 compliant
JTAG Boundary Scan — Yes, IEEE Std. 1149.1
Logic Family — CMOS
Process Technology — CMOS EEPROM

Datasheets & Resources

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