EPM3128ATC100-10N vs EPM3128ATC100-5 Comparison
Detailed side-by-side comparison of EPM3128ATC100-10N by Altera and EPM3128ATC100-5 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
EPM3128ATC100-10N NrndSpecification Comparison
| Parameter | EPM3128ATC100-10N | EPM3128ATC100-5 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.20 | $15.43 |
| Family | MAX 3000A | CPLD - MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Macro Cells | 128 | β |
| Usable Gates | 2500 | 2,500 |
| Number of I/O | 80 | β |
| Logic Elements / Blocks | 8 LABs (16 macrocells each) | β |
| Propagation Delay (tPD) | 10 ns | β |
| Maximum Internal Frequency (fMAX) | 98 MHz | β |
| Supply Voltage VCCINT | 3.3 V | β |
| I/O Bank Voltage VCCIO | 3.3 V or 2.5 V (selectable) | β |
| Configuration Memory | CMOS EEPROM (non-volatile, instant-on) | β |
| In-System Programming | IEEE Std. 1532-compliant ISP via JTAG | β |
| Package | 100-pin TQFP (14 x 14 x 1.0 mm) | 100-pin TQFP (Fine Line) |
| Operating Temperature | 0 Β°C to +70 Β°C (commercial) | 0 Β°C to 70 Β°C (Commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Compliant | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | β |
| MSL Level | 3 (per JEDEC J-STD-020) | β |
| Series | β | MAX 3000A |
| Macrocells | β | 128 |
| User I/Os | β | 80 |
| Dedicated Inputs | β | 4 |
| Pin-to-Pin Delay (tpd) | β | 5 ns (commercial); 7.5 ns |
| Maximum Frequency (fCNT) | β | 192.3 MHz |
| Supply Voltage (VCCINT/VCCIO) | β | 3.3 V |
| Output Drive Voltage | β | 2.5 V or 3.3 V (programmable) |
| Input Tolerance | β | 2.5 V, 3.3 V, 5.0 V tolerant |
| Program Memory Type | β | EEPROM |
| In-System Programmability | β | Yes, IEEE Std. 1532 compliant |
| JTAG Boundary Scan | β | Yes, IEEE Std. 1149.1 |
| Logic Family | β | CMOS |
| Process Technology | β | CMOS EEPROM |