EPM3128ATC100-5 - MAX 3000A CPLD, 128 Macrocells, 5ns TQFP-100
MPN: EPM3128ATC100-5 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $24.12 | $24.12 |
| 10 | $21.7 | $217.00 |
| 100 | $19.29 | $1,929.00 |
| 500 | $17.36 | $8,680.00 |
| 1,000 | $15.43 | $15,430.00 |
Drop-in alternatives for EPM3128ATC100-5 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM3128ATC100-7
β Drop-Inβ In Stock
$9.2 / Unit
View Datasheet βEPM3128ATC100-10N
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$5.2 / Unit
View Datasheet βEPM3128ATC100-10
β Drop-Inβ In Stock
$8.1 / Unit
View Datasheet βEPM3128ATC100-10NS
β Drop-Inβ In Stock
$6.5 / Unit
View Datasheet βEPM3128ATC100-10N
β Drop-Inβ In Stock
$5.2 / Unit
View Datasheet βEPM3128ATC100-5N
β Drop-Inβ In Stock
$8.2 / Unit
View Datasheet βEPM3128ATC100-5 Maximum Ratings & Electrical Characteristics
| Series | MAX 3000A |
| Family | CPLD - MAX 3000A |
| Macrocells | 128 |
| Usable Gates | 2,500 |
| User I/Os | 80 |
| Dedicated Inputs | 4 |
| Pin-to-Pin Delay (tpd) | 5 ns (commercial); 7.5 ns |
| Maximum Frequency (fCNT) | 192.3 MHz |
| Supply Voltage (VCCINT/VCCIO) | 3.3 V |
| Output Drive Voltage | 2.5 V or 3.3 V (programmable) |
| Input Tolerance | 2.5 V, 3.3 V, 5.0 V tolerant |
| Program Memory Type | EEPROM |
| In-System Programmability | Yes, IEEE Std. 1532 compliant |
| JTAG Boundary Scan | Yes, IEEE Std. 1149.1 |
| Operating Temperature | 0 Β°C to 70 Β°C (Commercial) |
| Package | 100-pin TQFP (Fine Line) |
| Mounting Type | Surface Mount |
| Logic Family | CMOS |
| Process Technology | CMOS EEPROM |
EPM3128ATC100-5 Pin Configuration
| Pin 1 | I/O β User I/O pin (pin numbers and assignments per MAX 3000A datasheet TQFP-100 pin table) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | VCCIO β I/O supply voltage (3.3 V) |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | I/O β User I/O pin |
| Pin 42 | VCCINT β Internal logic supply voltage (3.3 V) |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | GND β Ground |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | VCCIO β I/O supply voltage (3.3 V) |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | GND β Ground |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | I/O β User I/O pin |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | VCCINT β Internal logic supply voltage (3.3 V) |
| Pin 83 | I/O β User I/O pin |
| Pin 84 | I/O β User I/O pin |
| Pin 85 | I/O β User I/O pin |
| Pin 86 | I/O β User I/O pin |
| Pin 87 | I/O β User I/O pin |
| Pin 88 | I/O β User I/O pin |
| Pin 89 | I/O β User I/O pin |
| Pin 90 | I/O β User I/O pin |
| Pin 91 | I/O β User I/O pin |
| Pin 92 | GND β Ground |
| Pin 93 | IN4 β Dedicated input pin 4 |
| Pin 94 | IN3 β Dedicated input pin 3 |
| Pin 95 | IN2 β Dedicated input pin 2 |
| Pin 96 | IN1 β Dedicated input pin 1 |
| Pin 97 | TDI β JTAG Test Data In |
| Pin 98 | TMS β JTAG Test Mode Select |
| Pin 99 | TCK β JTAG Test Clock |
| Pin 100 | TDO β JTAG Test Data Out |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3128ATC100-5 is suitable for 6 applications: Bus Interface Bridging and Glue Logic, Address Decoding and Chip-Select Generation, State Machines and Sequencer Implementation, Mixed-Voltage Level Translation (5 V to 3.3 V), Legacy 74-Series TTL Replacement, Industrial Control and Factory Automation.
Bus Interface Bridging and Glue Logic
The EPM3128ATC100-5 is widely used as glue logic between microprocessors, memory, and peripheral buses in industrial and embedded designs. With 128 macrocells and 80 user I/Os, the device can implement address decoders, chip-select generators, wait-state controllers, and bus mux/demux functions in a single chip. Its 5 ns pin-to-pin delay meets the timing budget for PCI, ISA, and VMEbus bridges, where deterministic timing is essential. Compared to discrete 74-series TTL parts, it consumes less board area, reduces BOM cost, and is in-system reprogrammable for late-stage design changes.
Recommended
Address Decoding and Chip-Select Generation
The MAX 3000A architecture is optimized for wide AND-OR decode trees, making the EPM3128ATC100-5 ideal for address decoding in memory-mapped systems. The 128 macrocells can implement dozens of independent chip-select signals with full address-range decoding, even across 32-bit address buses. The 5 ns tPD ensures the chip-select assertion occurs well within one memory-access cycle. Designers typically program the device once via JTAG, then store the configuration in non-volatile EEPROM that loads instantly on power-up, with no boot delay.
Recommended
State Machines and Sequencer Implementation
Each EPM3128ATC100-5 macrocell contains a flip-flop programmable as D, T, JK, or SR with independent clock, clear, and preset controls. This makes the device excellent for implementing complex multi-state controllers such as motor-control state machines, communication protocol sequencers, and FPGA configuration controllers. With 192.3 MHz counter frequency and deterministic timing, the CPLD can drive high-bandwidth sequencing logic at full system clock rates. Designers can iterate state diagrams in MAX+PLUS II or Quartus II and reprogram in-circuit via JTAG.
Recommended
Mixed-Voltage Level Translation (5 V to 3.3 V)
The EPM3128ATC100-5 input pins accept 2.5 V, 3.3 V, and 5.0 V signals, while outputs are programmable to 2.5 V or 3.3 V. This allows the device to act as a bidirectional level translator between legacy 5 V peripherals and modern 3.3 V ASICs, microcontrollers, or FPGAs without external level-shifters. Up to 80 channels of translation can be implemented in a single device. The 5 ns propagation delay preserves timing margins in high-speed interfaces such as parallel ADC/DAC links, GPIO expansion buses, and legacy peripheral interconnects.
Recommended
Legacy 74-Series TTL Replacement
The EPM3128ATC100-5 can absorb the function of dozens of 74LS, 74HC, and 74FTC logic gates into a single device, dramatically reducing PCB area, power consumption, and assembly cost. With 128 macrocells, the device typically replaces 20-50 equivalent discrete SSI/MSI packages. Designers can drop in the CPLD with no changes to the board's signal routing - the same TQFP-100 footprint replaces a forest of SOIC packages. JTAG programming lets engineering teams refine logic without board respins.
Recommended
Industrial Control and Factory Automation
With its 80 user I/Os, deterministic 5 ns timing, and proven MAX 3000A architecture, the EPM3128ATC100-5 is found in PLC digital I/O modules, motor-drive interface boards, and process-control instruments. While the commercial-temperature grade (0 Β°C to 70 Β°C) limits it to controlled environments, the pin-compatible EPM3128ATC100-10N extends operation to industrial -40 Β°C to +85 Β°C. The CPLD handles encoder decoding, PWM generation, optocoupler interface, and emergency-stop logic in a single reprogrammable device, simplifying compliance with IEC 61131-2 industrial control standards.
Recommended
Recommended Products Summary
Engineering reference data for EPM3128ATC100-5 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3128ATC100-7 | EPM3128ATC100-10N | EPM3128ATC100-10 | EPM3128ATC100-10NS | EPM3128ATC100-5N |
|---|---|---|---|---|---|---|
| Package | TQFP-100 (Fine Line) | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same |
| Brand | Intel (formerly Altera) | Intel - same | Intel - same | Intel - same | Intel - same | Intel - same |
| Macrocells | 128 | 128 - same | 128 - same | 128 - same | 128 - same | 128 - same |
| Pin-to-Pin Delay (tPD) | 5 ns | 7.5 ns (slower) | 10 ns (slower) | 10 ns (slower) | 10 ns (slower) | 5 ns (identical) |
| User I/Os | 80 | 80 - same | 80 - same | 80 - same | 80 - same | 80 - same |
| Usable Gates | 2,500 | 2,500 - same | 2,500 - same | 2,500 - same | 2,500 - same | 2,500 - same |
| Supply Voltage | 3.3 V | 3.3 V - same | 3.3 V - same | 3.3 V - same | 3.3 V - same | 3.3 V - same |
| Operating Temperature | 0 to 70 Β°C (Commercial) | 0 to 70 Β°C (Commercial) | -40 to +85 Β°C (Industrial, N suffix = lead-free) | 0 to 70 Β°C (Commercial) | 0 to 70 Β°C (Commercial, NS suffix) | 0 to 70 Β°C (Commercial, N suffix = lead-free) |
| Lead-Free / RoHS | No (standard lead finish) | No | Yes (N suffix) | No | Yes (NS suffix) | Yes (N suffix) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Fastest MAX 3000A speed grade available (vs EPM3128ATC100-7)
- Identical die with lead-free / RoHS assembly (vs EPM3128ATC100-5N)
- Commercial temperature vs Industrial temperature grade (vs EPM3128ATC100-10N)
Design Notes
Estimated: the EPM3128ATC100-5 draws approximately 35-55 mA quiescent ICC at 3.3 V on VCCINT plus additional I/O VCCIO current proportional to switching frequency and load. Decouple each VCCINT and VCCIO pin with a 0.1 Β΅F X7R ceramic capacitor placed within 5 mm of the supply pin. Add a bulk 10 Β΅F tantalum or low-ESR ceramic near the device. The MAX 3000A family does not require power sequencing between VCCINT and VCCIO, but simultaneous ramp-up is recommended. In standby (no switching), the device draws under 5 mA - useful for battery-backed designs.
Use a 4-layer PCB with dedicated ground and power planes for designs exceeding 50 MHz internal frequencies. Route JTAG signals (TDI, TDO, TMS, TCK) with 4-6 mil traces and keep them away from fast-switching I/O. Add 4.7 kΞ© pull-ups on TMS and TDI to keep the JTAG state machine in a known state during power-up. Locate the device close to the JTAG header to minimize stub length; chained JTAG devices should share a common TCK with TDI/TDO daisy-chained. Keep I/O traces short (under 50 mm) for signals above 50 MHz to avoid reflections.
Three pitfalls are common when migrating the MAX 3000A design: (1) Quartus II dropped MAX 3000A support after v13.0 SP1 - if the original design file is unavailable, a fresh MAX+PLUS II license and legacy toolchain are required; (2) the ISP programming voltage is generated internally from VCC - external 12 V VPP is NOT required (unlike older MAX 5000/7000 devices); (3) the 'A' suffix (MAX 3000A) is NOT pin-compatible with the original MAX 3000 - the older MAX 3000 outputs were 5 V TTL, while MAX 3000A outputs are 2.5 V/3.3 V CMOS - replacing one with the other requires recompilation. Always verify the BSDL file matches the exact part number before JTAG boundary-scan testing.
Estimated: the TQFP-100 package has a typical ΞΈJA of approximately 45-55 Β°C/W (exact value depends on PCB copper area and airflow). With commercial 0-70 Β°C ambient and worst-case ICC of 150 mA, internal dissipation is roughly 0.5 W, giving a junction temperature rise of 22-28 Β°C above ambient - well within the 125 Β°C maximum. For industrial temperature variants (EPM3128ATC100-10N), ambient up to 85 Β°C is acceptable with similar copper area. No heatsink is required under any normal operating condition; however, the thermal performance improves dramatically with larger ground-plane copper on the top and bottom layers under the package.
Compliance Information
EPM3128ATC100-5 (non-N suffix) is the standard lead-bearing variant - NOT RoHS compliant. The EPM3128ATC100-5N suffix variant is the lead-free RoHS-compliant assembly of the same silicon. REACH, halogen-free, and conflict-mineral declarations are not present in the verified web data - all marked unknown.
