EPM3128ATC100-10N vs EPM3128ATC100-5 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3128ATC100-10N sa pamamagitan ng Altera at EPM3128ATC100-5 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
EPM3128ATC100-10N NrndPagsanggunian na paghahambing
| Parametro | EPM3128ATC100-10N | EPM3128ATC100-5 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 3000A | CPLD - MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | — |
| Usable Gates | 2500 | 2,500 |
| Number of I/O | 80 | — |
| Logic Elements / Blocks | 8 LABs (16 macrocells each) | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency (fMAX) | 98 MHz | — |
| Supply Voltage VCCINT | 3.3 V | — |
| I/O Bank Voltage VCCIO | 3.3 V or 2.5 V (selectable) | — |
| Configuration Memory | CMOS EEPROM (non-volatile, instant-on) | — |
| In-System Programming | IEEE Std. 1532-compliant ISP via JTAG | — |
| Packhaging | 100-pin TQFP (14 x 14 x 1.0 mm) | 100-pin TQFP (Fine Line) |
| Temperature na Operasyon | 0 °C to +70 °C (commercial) | 0 °C to 70 °C (Commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | — |
| Level ng MSL | 3 (per JEDEC J-STD-020) | — |
| Series | — | MAX 3000A |
| Macrocells | — | 128 |
| User I/Os | — | 80 |
| Dedicated Inputs | — | 4 |
| Pin-to-Pin Delay (tpd) | — | 5 ns (commercial); 7.5 ns |
| Maximum Frequency (fCNT) | — | 192.3 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 3.3 V |
| Output Drive Voltage | — | 2.5 V or 3.3 V (programmable) |
| Input Tolerance | — | 2.5 V, 3.3 V, 5.0 V tolerant |
| Program Memory Type | — | EEPROM |
| In-System Programmability | — | Yes, IEEE Std. 1532 compliant |
| JTAG Boundary Scan | — | Yes, IEEE Std. 1149.1 |
| Logic Family | — | CMOS |
| Process Technology | — | CMOS EEPROM |