EPM3256ATI144-7N vs EPM3256ATI144-10N Comparison

Detailed side-by-side comparison of EPM3256ATI144-7N by Altera and EPM3256ATI144-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3256ATI144-7N EPM3256ATI144-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $10.95 $10.25
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Macrocells 256 256
Usable Gates 5,000 5,000
Logic Array Blocks (LABs) 16 β€”
Maximum User I/O Pins 116 β€”
Propagation Delay (tPD) 7.5 ns (typical) 10 ns
Maximum Internal Frequency 126.6 MHz β€”
Core Supply Voltage (VCCINT) 3.3 V β€”
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V β€”
MultiVolt I/O Logic Levels 5.0 V / 3.3 V / 2.5 V β€”
Programming Technology EEPROM (in-system programmable) β€”
JTAG / ISP IEEE Std. 1532 compliant β€”
Boundary Scan IEEE Std. 1149.1 (JTAG) β€”
Hot-Socketing Support Yes β€”
Package TQFP-144 (20 x 20 mm, 0.5 mm pitch) 144-pin TQFP
Operating Temperature -40C to +85C (industrial) -40 C to +85 C (industrial, "I" suffix)
RoHS Status Compliant (lead-free) Compliant
User I/Os β€” 116
Logic Blocks / Logic Elements β€” 16
Max Frequency (fMAX) β€” 95.2 MHz
Supply Voltage - Core β€” 3.3 V
I/O Voltage Support β€” 1.8 V / 2.5 V / 3.3 V (multi-voltage)
In-System Programmability β€” Yes, IEEE Std. 1532 compliant
Boundary-Scan Test (BST) β€” Yes, IEEE Std. 1149.1 (JTAG)
Lead-Free / Pb-Free β€” Yes ("N" suffix)
Process Technology β€” CMOS EEPROM-based, non-volatile
Mounting Type β€” Surface Mount
MSL Level β€” 3 (per JEDEC J-STD-020, typical for TQFP)

Datasheets & Resources

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