EPM3512AFC256-20 vs EPM3512AFC256-10 Comparison
Detailed side-by-side comparison of EPM3512AFC256-20 by Altera and EPM3512AFC256-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AFC256-20 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-20 ObsoleteSpecification Comparison
| Parameter | EPM3512AFC256-20 | EPM3512AFC256-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Typical Usable Gates | 10,000 | — |
| Speed Grade | -20 (20 ns tPD) | — |
| Package | 256-ball FBGA (Fine-pitch BGA) | 256-pin FBGA |
| Pin Count | 256 | 256 |
| Operating Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Voltage (VCCIO) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| I/O Standards | LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant | — |
| Program Memory Type | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) |
| JTAG Support | Yes (boundary-scan + ISP) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | unknown |
| MSL Level | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Configuration Memory | Internal EEPROM | — |
| Logic Array Blocks (LABs) | — | 16 |
| Usable Gates | — | 10,000 |
| Maximum I/O Pins | — | 208 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 87 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5-V tolerant |
| Programmable Technology | — | CMOS EEPROM |
| Operating Temperature Range | — | [DATA_NEEDED: industrial/commercial operating temperature range] |
| Architecture | — | MAX (Multiple Array matriX) EEPROM-based |