EPM3512AFC256-20 vs EPM3512AFC256-23 Comparison
Detailed side-by-side comparison of EPM3512AFC256-20 by Altera and EPM3512AFC256-23 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AFC256-20 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-20 ObsoleteAltera
EPM3512AFC256-23 - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-23 ObsoleteSpecification Comparison
| Parameter | EPM3512AFC256-20 | EPM3512AFC256-23 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $15.75 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Typical Usable Gates | 10,000 | β |
| Speed Grade | -20 (20 ns tPD) | β |
| Package | 256-ball FBGA (Fine-pitch BGA) | 256-ball FineLine BGA (FC256), 17 mm x 17 mm |
| Pin Count | 256 | β |
| Operating Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | β |
| I/O Voltage (VCCIO) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | β |
| I/O Standards | LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant | β |
| Program Memory Type | EEPROM (non-volatile) | β |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | β |
| JTAG Support | Yes (boundary-scan + ISP) | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature grade] |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | β |
| MSL Level | [DATA_NEEDED: MSL moisture sensitivity level] | β |
| Configuration Memory | Internal EEPROM | β |
| Usable Gates | β | 10,000 |
| Logic Array Blocks (LABs) | β | 16 (32 macrocells each) |
| Maximum Operating Frequency | β | 178.6 MHz |
| Propagation Delay (tPD) | β | 5.5 ns |
| Pin-to-Pin Delay | β | 23 ns |
| Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Supply Voltage (VCCIO) | β | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| User I/O Pins | β | [DATA_NEEDED: user I/O count for FC256] |
| Programming Interface | β | JTAG (IEEE Std. 1149.1) / ISP |
| Process Technology | β | 0.30 Β΅m CMOS EEPROM |