EPM3512AFC256-20 vs EPM3512AFC256-23 Vergleich
Detaillierter Direktvergleich von EPM3512AFC256-20 von Altera und EPM3512AFC256-23 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM3512AFC256-20 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-20 ObsoleteAltera
EPM3512AFC256-23 - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-23 ObsoleteSpezifikationsvergleich
| Parameter | EPM3512AFC256-20 | EPM3512AFC256-23 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $15,75 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Typical Usable Gates | 10,000 | — |
| Speed Grade | -20 (20 ns tPD) | — |
| Gehäuse | 256-ball FBGA (Fine-pitch BGA) | 256-ball FineLine BGA (FC256), 17 mm x 17 mm |
| Pin-Anzahl | 256 | — |
| Operating Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Voltage (VCCIO) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| I/O Standards | LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant | — |
| Program Memory Type | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| JTAG Support | Yes (boundary-scan + ISP) | — |
| Montageart | Surface Mount | Surface Mount (BGA) |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature grade] |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | — |
| MSL-Level | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Configuration Memory | Internal EEPROM | — |
| Usable Gates | — | 10,000 |
| Logic Array Blocks (LABs) | — | 16 (32 macrocells each) |
| Maximum Operating Frequency | — | 178.6 MHz |
| Propagation Delay (tPD) | — | 5.5 ns |
| Pin-to-Pin Delay | — | 23 ns |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| User I/O Pins | — | [DATA_NEEDED: user I/O count for FC256] |
| Programming Interface | — | JTAG (IEEE Std. 1149.1) / ISP |
| Process Technology | — | 0.30 µm CMOS EEPROM |