EPM3512AFC256-23 vs EPM3512AFC256-10 Comparison
Detailed side-by-side comparison of EPM3512AFC256-23 by Altera and EPM3512AFC256-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AFC256-23 - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-23 Obsolete
Specification Comparison
| Parameter | EPM3512AFC256-23 | EPM3512AFC256-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.75 | $17.50 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10,000 |
| Logic Array Blocks (LABs) | 16 (32 macrocells each) | 16 |
| Maximum Operating Frequency | 178.6 MHz | β |
| Propagation Delay (tPD) | 5.5 ns | β |
| Pin-to-Pin Delay | 23 ns | β |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | β |
| User I/O Pins | [DATA_NEEDED: user I/O count for FC256] | β |
| Package | 256-ball FineLine BGA (FC256), 17 mm x 17 mm | 256-pin FBGA |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP | β |
| Process Technology | 0.30 Β΅m CMOS EEPROM | β |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | β |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| Maximum I/O Pins | β | 208 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Maximum Counter Frequency | β | 87 MHz |
| I/O Voltage Tolerance | β | 5-V tolerant |
| Programmable Technology | β | CMOS EEPROM |
| In-System Programmability | β | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) |
| Operating Temperature Range | β | [DATA_NEEDED: industrial/commercial operating temperature range] |
| Pin Count | β | 256 |
| RoHS Status | β | unknown |
| Architecture | β | MAX (Multiple Array matriX) EEPROM-based |