EPM3512AFC256-7 vs EPM3512AFC256-5C Comparison
Detailed side-by-side comparison of EPM3512AFC256-7 by Intel and EPM3512AFC256-5C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3512AFC256-7 - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel
EPM3512AFC256-7 ⚠ Last Time BuyAltera
EPM3512AFC256-5C - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-5C ObsoleteSpecification Comparison
| Parameter | EPM3512AFC256-7 | EPM3512AFC256-5C |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 212 | 212 (max) |
| Usable Gates | 10,000 | 10,000 |
| Pin-to-Pin Logic Delay | 7.5 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.0 V to 3.6 V (3.3 V typ.) | 3.3 V |
| I/O Voltage (VCCIO) | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O) |
| Package | 256-ball FineLine BGA (FBGA-256) | 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch |
| Programming | EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant) | — |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | 0 °C to +70 °C (commercial, "C" grade) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Configuration Memory | Non-volatile EEPROM | — |
| Maximum Operating Frequency | — | 95.2 MHz |
| Pin-to-Pin Delay (tPD) | — | 5 ns |
| Programming Interface | — | IEEE Std. 1532 / JTAG (4-wire) in-system programmable |
| Technology | — | EEPROM-based macrocell, non-volatile |