EPM3512AFC256-7 vs EPM3512AFC256-5C Perbandingan

Perbandingan bersamaan detil EPM3512AFC256-7 dari Intel dan EPM3512AFC256-5C dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Intel
EPM3512AFC256-7 EPM3512AFC256-7 - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel

EPM3512AFC256-7 - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel

EPM3512AFC256-7 ⚠ Waktu Beli Terakhir

Perbandingan Spesifikasi

Parameter Umum EPM3512AFC256-7 EPM3512AFC256-5C
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Waktu Pembelian Terakhir Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 512
Logic Array Blocks (LABs) 16 —
User I/O Pins 212 212 (max)
Usable Gates 10,000 10,000
Pin-to-Pin Logic Delay 7.5 ns —
Counter Frequency (max) 227.3 MHz —
Supply Voltage - Core (VCCINT) 3.0 V to 3.6 V (3.3 V typ.) 3.3 V
I/O Voltage (VCCIO) 5.0 V / 3.3 V / 2.5 V (MultiVolt) 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O)
Paket 256-ball FineLine BGA (FBGA-256) 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch
Programming EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant) —
Suhu Kerja [DATA_NEEDED: operating temperature grade] 0 °C to +70 °C (commercial, "C" grade)
Tipe Mounting Surface Mount Surface Mount
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Configuration Memory Non-volatile EEPROM —
Maximum Operating Frequency — 95.2 MHz
Pin-to-Pin Delay (tPD) — 5 ns
Programming Interface — IEEE Std. 1532 / JTAG (4-wire) in-system programmable
Technology — EEPROM-based macrocell, non-volatile

Spek dan Sumber

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