EPM3512AFI256-10 vs EPM3512AFI256-10N Comparison
Detailed side-by-side comparison of EPM3512AFI256-10 by Intel and EPM3512AFI256-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera
EPM3512AFI256-10N ⚠ Last Time BuySpecification Comparison
| Parameter | EPM3512AFI256-10 | EPM3512AFI256-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Last Time Buy |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Equivalent Gates | 10,000 | — |
| Macrocells | 512 | — |
| User I/Os | 208 | — |
| Pin-to-Pin Logic Delay (tPD) | 4.5 ns | — |
| Maximum Counter Frequency | 227.3 MHz | 227.3 MHz |
| Propagation Delay | 7.5 ns (max, per chipdig summary) | — |
| Core Voltage | 3.3 V | — |
| MultiVolt I/O Levels | 5.0 V / 3.3 V / 2.5 V | — |
| Process Technology | CMOS EEPROM | — |
| In-System Programmability | Yes, IEEE Std. 1532 (3.3 V ISP) | Yes - IEEE Std 1532 compliant |
| Package | FBGA-256 (FineLine BGA, 256 balls) | 256-ball FineLine BGA (FBGA-256) |
| Operating Temperature | 0C to +70C (commercial) | — |
| Logic Family | CMOS | — |
| RoHS Status | [DATA_NEEDED: rohs_status] | Compliant |
| Supply Voltage | 3.3 V (core); MultiVolt I/O to 5.0 V | — |
| Series | — | EPM3512 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | CMOS EEPROM-based, MAX architecture |
| Number of Macrocells | — | 512 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| Usable Gates | — | Up to 10,000 |
| Number of User I/O | — | 208 |
| Total Pins | — | 256 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Core Supply Voltage (VCCINT) | — | 3.3 V (3.0 V to 3.6 V) |
| I/O Supply Voltage (VCCIO) | — | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| MultiVolt I/O Support | — | 5.0 V / 3.3 V / 2.5 V |
| JTAG Boundary Scan | — | Yes - IEEE 1149.1 |
| Program Memory | — | EEPROM (non-volatile) |
| Mounting Type | — | Surface Mount |
| Operating Temperature Range | — | -40 °C to +85 °C (industrial) |
| Speed Grade | — | -10 (10 ns tPD) |