EPM3512AFI256-10 vs EPM3512AFI256-10N 对比

详细并排对比 EPM3512AFI256-10 出自 Intel 和 EPM3512AFI256-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Altera
EPM3512AFI256-10N EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera

EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera

EPM3512AFI256-10N ⚠ 最后一次采购

规格对比

参数 EPM3512AFI256-10 EPM3512AFI256-10N
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 最后采购期
库存状态 有库存 有库存
单价(USD) $18.75 $21.75
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Equivalent Gates 10,000 —
Macrocells 512 —
User I/Os 208 —
Pin-to-Pin Logic Delay (tPD) 4.5 ns —
Maximum Counter Frequency 227.3 MHz 227.3 MHz
Propagation Delay 7.5 ns (max, per chipdig summary) —
Core Voltage 3.3 V —
MultiVolt I/O Levels 5.0 V / 3.3 V / 2.5 V —
Process Technology CMOS EEPROM —
In-System Programmability Yes, IEEE Std. 1532 (3.3 V ISP) Yes - IEEE Std 1532 compliant
封装 FBGA-256 (FineLine BGA, 256 balls) 256-ball FineLine BGA (FBGA-256)
工作温度 0C to +70C (commercial) —
Logic Family CMOS —
RoHS 状态 [DATA_NEEDED: rohs_status] Compliant
电源电压 3.3 V (core); MultiVolt I/O to 5.0 V —
Series — EPM3512
Device Type — CPLD (Complex Programmable Logic Device)
Architecture — CMOS EEPROM-based, MAX architecture
Number of Macrocells — 512
Number of Logic Array Blocks (LABs) — 16
Usable Gates — Up to 10,000
Number of User I/O — 208
Total Pins — 256
Pin-to-Pin Propagation Delay (tPD) — 10 ns
Core Supply Voltage (VCCINT) — 3.3 V (3.0 V to 3.6 V)
I/O Supply Voltage (VCCIO) — 2.5 V or 3.3 V (5.0 V tolerant inputs)
MultiVolt I/O Support — 5.0 V / 3.3 V / 2.5 V
JTAG Boundary Scan — Yes - IEEE 1149.1
Program Memory — EEPROM (non-volatile)
安装类型 — Surface Mount
工作温度范围 — -40 °C to +85 °C (industrial)
Speed Grade — -10 (10 ns tPD)

数据手册与资源

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