EPM3512AQC208-10NS vs EPM3512AQC208-3N Comparison

Detailed side-by-side comparison of EPM3512AQC208-10NS by Altera and EPM3512AQC208-3N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-10NS EPM3512AQC208-3N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $32.40 $16.40
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macro Cells 512 β€”
Usable Gates 10,000 β€”
Logic Array Blocks (LABs) 12 16
User I/Os 172 β€”
Pin-to-Pin Delay (tPD) 10 ns (speed grade -10) β€”
Internal Counter Frequency 227.3 MHz max β€”
Propagation Delay 7.5 ns (datasheet figure) β€”
Core Supply Voltage (VCCINT) 3.3 V 3.3 V
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (MultiVolt) 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant)
Logic Family CMOS, EEPROM-based β€”
Configuration Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) β€”
Package 208-pin PQFP PQFP-208
Operating Temperature 0C to +70C (commercial) 0C to +70C (commercial)
ISP Standard IEEE Std. 1532 β€”
RoHS Status [DATA_NEEDED: rohs status] [DATA_NEEDED: not stated in retrieved snippets]
Mounting Type Surface Mount Surface Mount
Macrocells β€” 512
User I/O Pins β€” 172
Macrocells per LAB β€” 32
Pin-to-Pin Logic Delay β€” 3 ns (speed grade -3)
Global Clock Setup Time β€” [DATA_NEEDED: actual tSU at 3 ns grade]
Programming Technology β€” EEPROM (non-volatile, in-system programmable)
JTAG / Boundary Scan β€” IEEE 1149.1 compliant
ISP Compliance β€” IEEE Std. 1532
Lead-Free / Halogen-Free β€” [DATA_NEEDED]

Datasheets & Resources

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