EPM3512AQC208-10NS vs EPM3512AQC208-3N 比較
詳細な並列比較: EPM3512AQC208-10NS メーカー: Altera および EPM3512AQC208-3N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM3512AQC208-10NS | EPM3512AQC208-3N |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $32.40 | $16.40 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 512 | — |
| Usable Gates | 10,000 | — |
| Logic Array Blocks (LABs) | 12 | 16 |
| User I/Os | 172 | — |
| Pin-to-Pin Delay (tPD) | 10 ns (speed grade -10) | — |
| Internal Counter Frequency | 227.3 MHz max | — |
| Propagation Delay | 7.5 ns (datasheet figure) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant) |
| Logic Family | CMOS, EEPROM-based | — |
| Configuration | Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) | — |
| パッケージ | 208-pin PQFP | PQFP-208 |
| 動作温度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| ISP Standard | IEEE Std. 1532 | — |
| RoHS ステータス | [DATA_NEEDED: rohs status] | [DATA_NEEDED: not stated in retrieved snippets] |
| 実装タイプ | Surface Mount | Surface Mount |
| Macrocells | — | 512 |
| User I/O Pins | — | 172 |
| Macrocells per LAB | — | 32 |
| Pin-to-Pin Logic Delay | — | 3 ns (speed grade -3) |
| Global Clock Setup Time | — | [DATA_NEEDED: actual tSU at 3 ns grade] |
| Programming Technology | — | EEPROM (non-volatile, in-system programmable) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| ISP Compliance | — | IEEE Std. 1532 |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED] |