EPM5032DC-2 vs EPM5016DC-20 Comparison

Detailed side-by-side comparison of EPM5032DC-2 by Altera and EPM5016DC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5032DC-2 EPM5016DC-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Product Type CPLD (Complex Programmable Logic Device) —
Series MAX 5000 —
Macrocells 32 16
Usable Gates (typical) 600 —
Logic Array Blocks (LABs) 4 —
Package 20-pin CDIP (Ceramic DIP) —
Speed Grade -2 (tPD ~25 ns, commercial) -20 = 20 ns tPD
Configuration Memory EPROM (one-time programmable per generation; UV-erasable variants exist) —
Supply Voltage (VCC) 5 V (single supply, +/-5%) —
Operating Temperature 0C to +70C (commercial grade) [DATA_NEEDED: operating temperature range]
Programmable Pins / I/O 20 pins (JEDEC-standard 0.300" ceramic DIP) —
Programming Interface Altera ByteBlaster / parallel-port JTAG-style ISP —
Interconnect Programmable Interconnect Array (PIA) with deterministic timing —
RoHS Status [DATA_NEEDED: RoHS compliance - CDIP package typically pre-RoHS] [DATA_NEEDED: RoHS compliance]
Mounting Type Through-Hole (DIP) —
MSL Level Not applicable (through-hole hermetic ceramic) —
Family — MAX 5000
Device Type — EPLD (UV-Erasable Programmable Logic Device)
Product Terms — 160
Dedicated Inputs — 7
I/O Pins — 8
Propagation Delay (tPD) — 20 ns
Maximum Clock Frequency — 62.5 MHz
Maximum Supply Voltage — 5.25 V
Nominal Supply Voltage — 5.0 V
Process Technology — CMOS, UV-erasable
Architecture — PAL-type macrocell with Programmable Interconnect Array (PIA)
Package Type — 20-pin Ceramic DIP (Cerdip) with UV window
Package Suffix Code — DC = Ceramic DIP, Commercial
Programming Method — UV erase + EPROM-style programming via Altera programming hardware

Datasheets & Resources

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