EPM5032JC-20 vs EPM5032LC-20 Comparison
Detailed side-by-side comparison of EPM5032JC-20 by Altera and EPM5032LC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032JC-20 | EPM5032LC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | UV-erasable Programmable Logic Device (PLD) | EPLD / CPLD (One-Time Programmable / UV-Erasable) |
| Family | MAX 5000 | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | — |
| Product Terms (P-terms) | 320 | — |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Maximum Clock Frequency | 62.5 MHz | — |
| Setup Time | 10 ns | — |
| I/O Lines | 16 (bidirectional) | — |
| Dedicated Inputs | 8 | 7 |
| Total Inputs | 24 | 24 |
| Package | 68-pin JLCC (windowed ceramic) | LCC-28 (Plastic Leaded Chip Carrier, J-lead) |
| Process Technology | CMOS | — |
| Erase Method | UV (12V VPP + ultraviolet exposure) | — |
| Programming Voltage (VPP) | 12 V | — |
| Architecture | PAL-type AND-OR array with PIA interconnect | — |
| Lifecycle Status | Obsolete (legacy Altera MAX 5000) | — |
| Device Family | — | MAX 5000 |
| Usable Gates | — | 600 gates |
| Logic Blocks (LABs) | — | 1 |
| Speed Grade | — | -20 (20 ns pin-to-pin) |
| Maximum Frequency | — | 71.4 MHz |
| Supply Voltage (VCC) | — | 5 V ±5% |
| Operating Temperature | — | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) |
| Bidirectional I/O Pins | — | 16 |
| Output Functions | — | 16 |
| Product Terms per Output | — | 16 |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| Mounting Type | — | Surface Mount |
| RoHS Status | — | [DATA_NEEDED: RoHS status] |
| MSL Level | — | [DATA_NEEDED: MSL] |