EPM5032JC-20 vs EPM5032LC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032JC-20 sa pamamagitan ng Altera at EPM5032LC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032JC-20 | EPM5032LC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | UV-erasable Programmable Logic Device (PLD) | EPLD / CPLD (One-Time Programmable / UV-Erasable) |
| Family | MAX 5000 | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | — |
| Product Terms (P-terms) | 320 | — |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Maksimum na Taktiko ng Oras | 62.5 MHz | — |
| Setup Time | 10 ns | — |
| I/O Lines | 16 (bidirectional) | — |
| Dedicated Inputs | 8 | 7 |
| Total Inputs | 24 | 24 |
| Packhaging | 68-pin JLCC (windowed ceramic) | LCC-28 (Plastic Leaded Chip Carrier, J-lead) |
| Process Technology | CMOS | — |
| Erase Method | UV (12V VPP + ultraviolet exposure) | — |
| Programming Voltage (VPP) | 12 V | — |
| Architecture | PAL-type AND-OR array with PIA interconnect | — |
| Katayuan ng Lifecycle | Obsolete (legacy Altera MAX 5000) | — |
| Device Family | — | MAX 5000 |
| Usable Gates | — | 600 gates |
| Logic Blocks (LABs) | — | 1 |
| Speed Grade | — | -20 (20 ns pin-to-pin) |
| Maximum Frequency | — | 71.4 MHz |
| Supply Voltage (VCC) | — | 5 V ±5% |
| Temperature na Operasyon | — | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) |
| Bidirectional I/O Pins | — | 16 |
| Output Functions | — | 16 |
| Product Terms per Output | — | 16 |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| Uri ng Pagpapasok | — | Surface Mount |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |
| Level ng MSL | — | [DATA_NEEDED: MSL] |