EPM5032JC-20 vs EPM5032PC-20 Comparison
Detailed side-by-side comparison of EPM5032JC-20 by Altera and EPM5032PC-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032JC-20 | EPM5032PC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | UV-erasable Programmable Logic Device (PLD) | — |
| Family | MAX 5000 | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | — |
| Product Terms (P-terms) | 320 | — |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Maximum Clock Frequency | 62.5 MHz | 62.5 MHz |
| Setup Time | 10 ns | — |
| I/O Lines | 16 (bidirectional) | — |
| Dedicated Inputs | 8 | 24 |
| Total Inputs | 24 | — |
| Package | 68-pin JLCC (windowed ceramic) | PDIP-28 (Plastic DIP, 28-pin) |
| Process Technology | CMOS | — |
| Erase Method | UV (12V VPP + ultraviolet exposure) | — |
| Programming Voltage (VPP) | 12 V | — |
| Architecture | PAL-type AND-OR array with PIA interconnect | PAL-type macrocells with Programmable Interconnect Array (PIA) |
| Lifecycle Status | Obsolete (legacy Altera MAX 5000) | — |
| Device Family | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Programming Type | — | OTP (One-Time Programmable) |
| Usable Gates | — | 600 |
| Logic Blocks | — | 2 Logic Array Blocks |
| Product Terms | — | 320 |
| Bidirectional I/O Lines | — | 16 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| Technology | — | CMOS, 0.65 um process |
| Operating Temperature | — | [DATA_NEEDED: operating temperature range] |
| Mounting Type | — | Through-Hole |
| RoHS Status | — | [DATA_NEEDED: RoHS status] |