EPM5032JC-20 vs EPM5032PC-20 Vergleich
Detaillierter Direktvergleich von EPM5032JC-20 von Altera und EPM5032PC-20 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5032JC-20 | EPM5032PC-20 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $7,05 |
| Product Type | UV-erasable Programmable Logic Device (PLD) | — |
| Family | MAX 5000 | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | — |
| Product Terms (P-terms) | 320 | — |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Maximale Taktfrequenz | 62.5 MHz | 62.5 MHz |
| Setup Time | 10 ns | — |
| I/O Lines | 16 (bidirectional) | — |
| Dedicated Inputs | 8 | 24 |
| Total Inputs | 24 | — |
| Gehäuse | 68-pin JLCC (windowed ceramic) | PDIP-28 (Plastic DIP, 28-pin) |
| Process Technology | CMOS | — |
| Erase Method | UV (12V VPP + ultraviolet exposure) | — |
| Programming Voltage (VPP) | 12 V | — |
| Architecture | PAL-type AND-OR array with PIA interconnect | PAL-type macrocells with Programmable Interconnect Array (PIA) |
| Lebenszyklusstatus | Obsolete (legacy Altera MAX 5000) | — |
| Device Family | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Programming Type | — | OTP (One-Time Programmable) |
| Usable Gates | — | 600 |
| Logic Blocks | — | 2 Logic Array Blocks |
| Product Terms | — | 320 |
| Bidirectional I/O Lines | — | 16 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| Technology | — | CMOS, 0.65 um process |
| Betriebstemperatur | — | [DATA_NEEDED: operating temperature range] |
| Montageart | — | Through-Hole |
| RoHS-Status | — | [DATA_NEEDED: RoHS status] |