EPM5032JC-20 vs EPM5032PC-20 比較
詳細な並列比較: EPM5032JC-20 メーカー: Altera および EPM5032PC-20 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5032JC-20 | EPM5032PC-20 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.75 | $7.05 |
| Product Type | UV-erasable Programmable Logic Device (PLD) | — |
| Family | MAX 5000 | — |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | — |
| Product Terms (P-terms) | 320 | — |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| 最大クロック周波数 | 62.5 MHz | 62.5 MHz |
| Setup Time | 10 ns | — |
| I/O Lines | 16 (bidirectional) | — |
| Dedicated Inputs | 8 | 24 |
| Total Inputs | 24 | — |
| パッケージ | 68-pin JLCC (windowed ceramic) | PDIP-28 (Plastic DIP, 28-pin) |
| Process Technology | CMOS | — |
| Erase Method | UV (12V VPP + ultraviolet exposure) | — |
| Programming Voltage (VPP) | 12 V | — |
| Architecture | PAL-type AND-OR array with PIA interconnect | PAL-type macrocells with Programmable Interconnect Array (PIA) |
| ライフサイクル状態 | Obsolete (legacy Altera MAX 5000) | — |
| Device Family | — | MAX 5000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Programming Type | — | OTP (One-Time Programmable) |
| Usable Gates | — | 600 |
| Logic Blocks | — | 2 Logic Array Blocks |
| Product Terms | — | 320 |
| Bidirectional I/O Lines | — | 16 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| Technology | — | CMOS, 0.65 um process |
| 動作温度 | — | [DATA_NEEDED: operating temperature range] |
| 実装タイプ | — | Through-Hole |
| RoHS ステータス | — | [DATA_NEEDED: RoHS status] |